* Barebox for Zedboard
@ 2020-03-19 10:38 Michael Graichen
2020-03-19 10:53 ` Lucas Stach
0 siblings, 1 reply; 6+ messages in thread
From: Michael Graichen @ 2020-03-19 10:38 UTC (permalink / raw)
To: barebox
Hey,
i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC.
I have seen that Barebox has an defconfig for the zynq
so i tried
export ARCH=arm
export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf-
export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH
make zynq_defconfig
make -j`nproc`
which compiles me the image
barebox-flash-image -> images/barebox-avnet-zedboard.img
when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool
dev$ bootgen -image bootimage.bif -o i BOOT.bin
and .bif file was
dev$ cat bootimage.bif
//arch = zynq; split = false; format = BIN
the_ROM_image:
{
[bootloader]FSBL.elf
design_1_wrapper.bit
u-boot.elf
}
that i copied onto an SD-Card and powed up the board.
But since i want to use Barebox how do i produce the BOOT.bin file?
and how is the programming of the FPGA Logic done?
Best Regards
Michael
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barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: Barebox for Zedboard 2020-03-19 10:38 Barebox for Zedboard Michael Graichen @ 2020-03-19 10:53 ` Lucas Stach 2020-03-23 14:22 ` AW: " Michael Graichen 2020-03-23 15:18 ` Michael Graichen 0 siblings, 2 replies; 6+ messages in thread From: Lucas Stach @ 2020-03-19 10:53 UTC (permalink / raw) To: Michael Graichen, barebox Hi Michael, Am Donnerstag, den 19.03.2020, 10:38 +0000 schrieb Michael Graichen: > Hey, > > i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC. > I have seen that Barebox has an defconfig for the zynq > so i tried > > export ARCH=arm > export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf- > export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH > make zynq_defconfig > make -j`nproc` > > which compiles me the image > > barebox-flash-image -> images/barebox-avnet-zedboard.img > > when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool > > dev$ bootgen -image bootimage.bif -o i BOOT.bin > > and .bif file was > > dev$ cat bootimage.bif > //arch = zynq; split = false; format = BIN > the_ROM_image: > { > [bootloader]FSBL.elf > design_1_wrapper.bit > u-boot.elf > } > > > that i copied onto an SD-Card and powed up the board. > > But since i want to use Barebox how do i produce the BOOT.bin file? The barebox-avnet-zedboard.img already is the BOOT.bin image, just copy it to the SD card with this name and you are done. > and how is the programming of the FPGA Logic done? Barebox currently doesn't support loading the FPGA bitstream. We are still lacking a driver for the DevC PCAP interface. Zynq support in Barebox is only a spare time (and thus toy) project at this time. It works okay for booting Linux on the PS part of the system, but almost fully lacks support for the PL part. That said I wouldn't mind helping with getting the missing bits added by reviewing/testing patches. :) Regards, Lucas _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* AW: Barebox for Zedboard 2020-03-19 10:53 ` Lucas Stach @ 2020-03-23 14:22 ` Michael Graichen 2020-03-23 15:18 ` Michael Graichen 1 sibling, 0 replies; 6+ messages in thread From: Michael Graichen @ 2020-03-23 14:22 UTC (permalink / raw) To: Lucas Stach, barebox ________________________________________ Von: Lucas Stach <l.stach@pengutronix.de> Gesendet: Donnerstag, 19. März 2020 11:53 An: Michael Graichen; barebox@lists.infradead.org Betreff: Re: Barebox for Zedboard Hi Michael, Am Donnerstag, den 19.03.2020, 10:38 +0000 schrieb Michael Graichen: > Hey, > > i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC. > I have seen that Barebox has an defconfig for the zynq > so i tried > > export ARCH=arm > export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf- > export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH > make zynq_defconfig > make -j`nproc` > > which compiles me the image > > barebox-flash-image -> images/barebox-avnet-zedboard.img > > when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool > > dev$ bootgen -image bootimage.bif -o i BOOT.bin > > and .bif file was > > dev$ cat bootimage.bif > //arch = zynq; split = false; format = BIN > the_ROM_image: > { > [bootloader]FSBL.elf > design_1_wrapper.bit > u-boot.elf > } > > > that i copied onto an SD-Card and powed up the board. > > But since i want to use Barebox how do i produce the BOOT.bin file? The barebox-avnet-zedboard.img already is the BOOT.bin image, just copy it to the SD card with this name and you are done. > and how is the programming of the FPGA Logic done? Barebox currently doesn't support loading the FPGA bitstream. We are still lacking a driver for the DevC PCAP interface. Zynq support in Barebox is only a spare time (and thus toy) project at this time. It works okay for booting Linux on the PS part of the system, but almost fully lacks support for the PL part. That said I wouldn't mind helping with getting the missing bits added by reviewing/testing patches. :) Regards, Lucas Hey Lucas, thanks for your reply. for some reason i had to comment out everything that is in arch/arm/boards/avnet-zedboard/zedboard.zynqcfg besides the last line wm 32 0xffffffff 0x00000000 to get a working Bootloader. https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf tells me that these values are suposed to be set by the BootROM and 0xffffffff signals the end of the list but unfortunatly the boot process hangs here when the unlock value is written. So i decided to leave this list empty. Has anybody seen a similar behaviour? Best regards Michael _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* AW: Barebox for Zedboard 2020-03-19 10:53 ` Lucas Stach 2020-03-23 14:22 ` AW: " Michael Graichen @ 2020-03-23 15:18 ` Michael Graichen 2025-05-16 19:03 ` Johannes Roith 1 sibling, 1 reply; 6+ messages in thread From: Michael Graichen @ 2020-03-23 15:18 UTC (permalink / raw) To: Lucas Stach, barebox ________________________________________ Von: Lucas Stach <l.stach@pengutronix.de> Gesendet: Donnerstag, 19. März 2020 11:53 An: Michael Graichen; barebox@lists.infradead.org Betreff: Re: Barebox for Zedboard Hi Michael, Am Donnerstag, den 19.03.2020, 10:38 +0000 schrieb Michael Graichen: > Hey, > > i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC. > I have seen that Barebox has an defconfig for the zynq > so i tried > > export ARCH=arm > export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf- > export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH > make zynq_defconfig > make -j`nproc` > > which compiles me the image > > barebox-flash-image -> images/barebox-avnet-zedboard.img > > when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool > > dev$ bootgen -image bootimage.bif -o i BOOT.bin > > and .bif file was > > dev$ cat bootimage.bif > //arch = zynq; split = false; format = BIN > the_ROM_image: > { > [bootloader]FSBL.elf > design_1_wrapper.bit > u-boot.elf > } > > > that i copied onto an SD-Card and powed up the board. > > But since i want to use Barebox how do i produce the BOOT.bin file? The barebox-avnet-zedboard.img already is the BOOT.bin image, just copy it to the SD card with this name and you are done. > and how is the programming of the FPGA Logic done? Barebox currently doesn't support loading the FPGA bitstream. We are still lacking a driver for the DevC PCAP interface. Zynq support in Barebox is only a spare time (and thus toy) project at this time. It works okay for booting Linux on the PS part of the system, but almost fully lacks support for the PL part. That said I wouldn't mind helping with getting the missing bits added by reviewing/testing patches. :) Regards, Lucas Hey Lucas, "That said I wouldn't mind helping with getting the missing bits added by reviewing/testing patches. :)" Did you made any attempts to do this? As far as I can see there are basicly two ways. The "Xilinx-Way" by packing everything in Boot.bin. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841976/Prepare+boot+image and the "Linux-Way" https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager using the FPGA manager https://elixir.bootlin.com/linux/latest/source/drivers/fpga/zynq-fpga.c Best regards Michael _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Barebox for Zedboard 2020-03-23 15:18 ` Michael Graichen @ 2025-05-16 19:03 ` Johannes Roith 2025-05-16 19:28 ` Ahmad Fatoum 0 siblings, 1 reply; 6+ messages in thread From: Johannes Roith @ 2025-05-16 19:03 UTC (permalink / raw) To: Michael Graichen; +Cc: barebox Am Mon, Mar 23, 2020 at 03:18:22PM +0000 schrieb Michael Graichen: Hi Michael, hi Lucas, > > ________________________________________ > Von: Lucas Stach <l.stach@pengutronix.de> > Gesendet: Donnerstag, 19. März 2020 11:53 > An: Michael Graichen; barebox@lists.infradead.org > Betreff: Re: Barebox for Zedboard > > Hi Michael, > > Am Donnerstag, den 19.03.2020, 10:38 +0000 schrieb Michael Graichen: > > Hey, > > > > i have just started working on a Zedboard (http://zedboard.org/product/zedboard) with an Xilinx Zynq XC7Z020 SOC. > > I have seen that Barebox has an defconfig for the zynq > > so i tried > > > > export ARCH=arm > > export CROSS_COMPILE=arm-cortexa9-linux-gnueabihf- > > export PATH=/opt/OSELAS.Toolchain/arm-cortexa9-linux-gnueabihf/bin:$PATH > > make zynq_defconfig > > make -j`nproc` > > > > which compiles me the image > > > > barebox-flash-image -> images/barebox-avnet-zedboard.img > > > > when using u-boot i had to generate a BOOT.bin file with Xilinx's ./bootgen tool > > > > dev$ bootgen -image bootimage.bif -o i BOOT.bin > > > > and .bif file was > > > > dev$ cat bootimage.bif > > //arch = zynq; split = false; format = BIN > > the_ROM_image: > > { > > [bootloader]FSBL.elf > > design_1_wrapper.bit > > u-boot.elf > > } > > > > > > that i copied onto an SD-Card and powed up the board. > > > > But since i want to use Barebox how do i produce the BOOT.bin file? > > The barebox-avnet-zedboard.img already is the BOOT.bin image, just copy > it to the SD card with this name and you are done. > > > and how is the programming of the FPGA Logic done? Michael, did you implement something here? In the latest barebox version I can't find anything related to FPGA loading. But if you have developed something and you could share it, it would be interesting for me and highly appreciated. > > Barebox currently doesn't support loading the FPGA bitstream. We are > still lacking a driver for the DevC PCAP interface. Zynq support in > Barebox is only a spare time (and thus toy) project at this time. It > works okay for booting Linux on the PS part of the system, but almost > fully lacks support for the PL part. I would like to try bringing PL support to barebox, but I need a bit of guidance. In the Linux kernel there are drivers available for the ZYNQ FPGA and there is the FPGA manager. As barebox "reuses" Linux drivers maybe that would be the way to go. I would love to have one barebox command available to load a bitstream to the PL. For doing so I would need to implement a fpgamgr-lib where I provide the interfaces used by the Linux FPGA drivers. The drivers also need to be modified a bit. Then finally I can implement the command. Am I missing something? Do you have any advice or sample code I could take a look at or use for orientation? Any comments are welcome. The big advantage of using such an approach would be support for similar devices (e.g. the UltraScale+ ZYNQMP devices) could be added easily by porting the Linux drivers to barebox. > > That said I wouldn't mind helping with getting the missing bits added > by reviewing/testing patches. :) > > Regards, > Lucas > > Hey Lucas, > > "That said I wouldn't mind helping with getting the missing bits added > by reviewing/testing patches. :)" > > Did you made any attempts to do this? > > As far as I can see there are basicly two ways. > The "Xilinx-Way" by packing everything in Boot.bin. > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841976/Prepare+boot+image > and the "Linux-Way" > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager > using the FPGA manager > https://elixir.bootlin.com/linux/latest/source/drivers/fpga/zynq-fpga.c > > Best regards > Michael > > > > > > > > > _______________________________________________ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox Best regards, Johannes ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Barebox for Zedboard 2025-05-16 19:03 ` Johannes Roith @ 2025-05-16 19:28 ` Ahmad Fatoum 0 siblings, 0 replies; 6+ messages in thread From: Ahmad Fatoum @ 2025-05-16 19:28 UTC (permalink / raw) To: Johannes Roith, Michael Graichen; +Cc: barebox Hello Johannes, On 16.05.25 21:03, Johannes Roith wrote: > The big advantage of using such an approach would be support for similar > devices (e.g. the UltraScale+ ZYNQMP devices) could be added easily by > porting the Linux drivers to barebox. I can't comment on the Zynq, but for ZynqMP, there is already a FPGA manager driver in drivers/firmware/zynqmp-fpga.c. FPGA programming is also supported for Altera SoCFPGA and are exposed over the firmware API. Loading OF overlays can already load firmware that way. Cheers, Ahmad >> That said I wouldn't mind helping with getting the missing bits added >> by reviewing/testing patches. :) >> >> Regards, >> Lucas >> >> Hey Lucas, >> >> "That said I wouldn't mind helping with getting the missing bits added >> by reviewing/testing patches. :)" >> >> Did you made any attempts to do this? >> >> As far as I can see there are basicly two ways. >> The "Xilinx-Way" by packing everything in Boot.bin. >> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841976/Prepare+boot+image >> and the "Linux-Way" >> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager >> using the FPGA manager >> https://elixir.bootlin.com/linux/latest/source/drivers/fpga/zynq-fpga.c >> >> Best regards >> Michael >> >> >> >> >> >> >> >> >> _______________________________________________ >> barebox mailing list >> barebox@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/barebox > > Best regards, > Johannes > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-05-16 19:28 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-03-19 10:38 Barebox for Zedboard Michael Graichen 2020-03-19 10:53 ` Lucas Stach 2020-03-23 14:22 ` AW: " Michael Graichen 2020-03-23 15:18 ` Michael Graichen 2025-05-16 19:03 ` Johannes Roith 2025-05-16 19:28 ` Ahmad Fatoum
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