Re: Enclustra SA2: enable dual fast Ethernet

[Oleksij Rempel <o.rempel@pengutronix.de>]

Hi David,

Ethernet is usually my playground, so I'll answer here as far as I can
:)

On Wed, Mar 25, 2026 at 05:13:52PM +0100, David Picard wrote:
> Hello,
> 
> I am still using the same Mercury_SA2_ST1_Reference_Design [1][2] released
> by the manufacturer:
> https://github.com/enclustra/Mercury_SA2_ST1_Reference_Design.git
> 
> But I compiled a variant of the project to enable dual fast Ethernet,
> because I need a 2nd Ethernet interface.

> SA2 module Ethernet layout:
> - 1 Ethernet MAC ("gmac1" in the DTS) of the HPS [3] is used for gigabit
> Ethernet, and connects with RGMII to PHY at address 3 >> working!
> - 2 Ethernet MACs are implemented as FPGA IP cores and connect with RMII to
> PHYs at addresses 1 and 2 >> to be configured...
> 
> All 3 PHYs share the same MDIO bus.

In this case barebox will need to resolve all pre-dependencies in the
correct order, which make things tricky:
- FPGA MACs should be probed after MDIO bus was scanned and PHYs
  detected. If PHY resets are asserted, we need to deasserted them in
  software, before MDIO bus scan.
- if MDIO bus is a part of the gmac1 block and driver, then this one
  should be probed as the first one in the chain.
- except of resets and MDIO bus, we need also clocks for the PHYs and
  and MACs.

As soon as all related topology is reconstructed in the correct order,
it will magically work :D

> I generated a DTS file with Intel's tool:
> $ sopc2dts --force-altr -t dts -i
> ./Quartus/ME-SA2-D6-7I-D11-DFE/sdmmc/Mercury_SA2_pd.sopcinfo -o
> Mercury_SA2_pd.dts
> 
> The file is here [4]:
> https://filesender.renater.fr/?s=download&token=b2eeab16-063c-41ef-8abe-ea5b44f8f25a&lang=en

Hm, i see some MACs, but no PHY configurations in attached devicetree.
PHYs should be properly described with resets and MAC <> PHY linkage.

> Now, I am trying to merge the fast Ethernet section with the
> socfpga_cyclone5_mercury_sa2.dtsi, but I really need a hint, here...
> https://git.pengutronix.de/cgit/barebox/tree/arch/arm/dts/socfpga_cyclone5_mercury_sa2.dtsi
> https://git.pengutronix.de/cgit/barebox/tree/dts/src/arm/intel/socfpga/socfpga.dtsi
> 
> However, I do know for a fact that the 2 PHYs at addresses 1 and 2 share the
> same reset pin and can be released from reset by:
> reset-gpios = <&portb 6 GPIO_ACTIVE_LOW>;

Shared reset for PHYs is not very nice design :)  Some times PHYs need
to be reset for each link up/down cycle. A shared reset makes it
impossible.

Best Regards,
Oleksij
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