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* [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register
       [not found] <1402045936-18733-1-git-send-email-matteo.fortini@gmail.com>
@ 2014-06-06  9:12 ` Matteo Fortini
  2014-06-10  6:33   ` Sascha Hauer
  2014-06-06  9:12 ` [PATCH 2/2] sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot Matteo Fortini
  1 sibling, 1 reply; 5+ messages in thread
From: Matteo Fortini @ 2014-06-06  9:12 UTC (permalink / raw)
  To: barebox

As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
MODE register has offset 0x10 and at offset 0x0C there is
a TIMINGS register.

Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
---
 arch/arm/mach-at91/include/mach/at91sam9_smc.h | 31 +++++++++++++++++++++++++-
 arch/arm/mach-at91/sam9_smc.c                  | 19 ++++++++++++++++
 2 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index d5cf5f7..6412664 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -43,6 +43,16 @@ struct sam9_smc_config {
 	/* Mode register */
 	u32 mode;
 	u8 tdf_cycles:4;
+
+	/* Timings register */
+	u8 tclr;
+	u8 tadl;
+	u8 tar;
+	u8 ocms;
+	u8 trr;
+	u8 twb;
+	u8 rbnsel;
+	u8 nfsel;
 };
 
 extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
@@ -77,7 +87,25 @@ extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
 #define		AT91_SMC_NRDCYCLE	(0x1ff << 16)			/* Total Read Cycle Length */
 #define			AT91_SMC_NRDCYCLE_(x)	((x) << 16)
 
-#define AT91_SMC_MODE		0x0c				/* Mode Register for CS n */
+#define AT91_SMC_TIMINGS	0x0c				/* Timings register for CS n */
+#define		AT91_SMC_TCLR		(0x0f  <<  0)			/* CLE to REN Low Delay */
+#define			AT91_SMC_TCLR_(x)	((x) << 0)
+#define		AT91_SMC_TADL		(0x0f  <<  4)			/* ALE to Data Start */
+#define			AT91_SMC_TADL_(x)	((x) << 4)
+#define		AT91_SMC_TAR		(0x0f  <<  8)			/* ALE to REN Low Delay */
+#define			AT91_SMC_TAR_(x)	((x) << 8)
+#define		AT91_SMC_OCMS		(0x1   << 12)			/* Off Chip Memory Scrambling Enable */
+#define			AT91_SMC_OCMS_(x)	((x) << 12)
+#define		AT91_SMC_TRR		(0x0f  << 16)			/* Ready to REN Low Delay */
+#define			AT91_SMC_TRR_(x)        ((x) << 16)
+#define		AT91_SMC_TWB		(0x0f  << 24)			/* WEN High to REN to Busy */
+#define			AT91_SMC_TWB_(x)	((x) << 24)
+#define		AT91_SMC_RBNSEL		(0x07  << 28)			/* Ready/Busy Line Selection */
+#define			AT91_SMC_RBNSEL_(x)	((x) << 28)
+#define		AT91_SMC_NFSEL		(0x01  << 31)			/* Nand Flash Selection */
+#define			AT91_SMC_NFSEL_(x)	((x) << 31)
+
+#define AT91_SMC_MODE		((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? 0x10 : 0x0c)				/* Mode Register for CS n */
 #define		AT91_SMC_READMODE	(1 <<  0)			/* Read Mode */
 #define		AT91_SMC_WRITEMODE	(1 <<  1)			/* Write Mode */
 #define		AT91_SMC_EXNWMODE	(3 <<  4)			/* NWAIT Mode */
@@ -101,4 +129,5 @@ extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
 #define			AT91_SMC_PS_16			(2 << 28)
 #define			AT91_SMC_PS_32			(3 << 28)
 
+
 #endif
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index c7bfdfd..89f73ef 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -30,6 +30,20 @@ static void sam9_smc_cs_write_mode(void __iomem *base,
 		   base + AT91_SMC_MODE);
 }
 
+static void sam9_smc_cs_write_timings(void __iomem *base,
+					struct sam9_smc_config *config)
+{
+	__raw_writel(AT91_SMC_TCLR_(config->tclr)
+                   | AT91_SMC_TADL_(config->tadl)
+                   | AT91_SMC_TAR_(config->tar)
+                   | AT91_SMC_OCMS_(config->ocms)
+                   | AT91_SMC_TRR_(config->trr)
+                   | AT91_SMC_TWB_(config->twb)
+                   | AT91_SMC_RBNSEL_(config->rbnsel)
+                   | AT91_SMC_NFSEL_(config->nfsel),
+		   base + AT91_SMC_TIMINGS);
+}
+
 void sam9_smc_write_mode(int id, int cs,
 					struct sam9_smc_config *config)
 {
@@ -61,6 +75,11 @@ static void sam9_smc_cs_configure(void __iomem *base,
 
 	/* Mode register */
 	sam9_smc_cs_write_mode(base, config);
+
+	/* Timings register */
+	if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
+		sam9_smc_cs_write_timings(base, config);
+	}
 }
 
 void sam9_smc_configure(int id, int cs,
-- 
2.0.0.rc2


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^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH 2/2] sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot
       [not found] <1402045936-18733-1-git-send-email-matteo.fortini@gmail.com>
  2014-06-06  9:12 ` [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register Matteo Fortini
@ 2014-06-06  9:12 ` Matteo Fortini
  1 sibling, 0 replies; 5+ messages in thread
From: Matteo Fortini @ 2014-06-06  9:12 UTC (permalink / raw)
  To: barebox

The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization

Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
---
 arch/arm/boards/sama5d3xek/init.c | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c
index e078642..0d1b459 100644
--- a/arch/arm/boards/sama5d3xek/init.c
+++ b/arch/arm/boards/sama5d3xek/init.c
@@ -72,21 +72,29 @@ static struct atmel_nand_data nand_pdata = {
 };
 
 static struct sam9_smc_config cm_nand_smc_config = {
-	.ncs_read_setup		= 0,
-	.nrd_setup		= 1,
-	.ncs_write_setup	= 0,
-	.nwe_setup		= 1,
+	.ncs_read_setup		= 1,
+	.nrd_setup		= 2,
+	.ncs_write_setup	= 1,
+	.nwe_setup		= 2,
 
-	.ncs_read_pulse		= 6,
-	.nrd_pulse		= 4,
+	.ncs_read_pulse		= 5,
+	.nrd_pulse		= 3,
 	.ncs_write_pulse	= 5,
 	.nwe_pulse		= 3,
 
-	.read_cycle		= 6,
-	.write_cycle		= 5,
+	.read_cycle		= 8,
+	.write_cycle		= 8,
 
 	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-	.tdf_cycles		= 1,
+	.tdf_cycles		= 3,
+	.tclr			= 3,
+	.tadl			= 10,
+	.tar			= 3,
+	.ocms			= 0,
+	.trr			= 4,
+	.twb			= 5,
+	.rbnsel			= 3,
+	.nfsel			= 1
 };
 
 static void ek_add_device_nand(void)
-- 
2.0.0.rc2


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^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register
  2014-06-06  9:12 ` [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register Matteo Fortini
@ 2014-06-10  6:33   ` Sascha Hauer
  0 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2014-06-10  6:33 UTC (permalink / raw)
  To: Matteo Fortini; +Cc: barebox

On Fri, Jun 06, 2014 at 11:12:15AM +0200, Matteo Fortini wrote:
> As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
> MODE register has offset 0x10 and at offset 0x0C there is
> a TIMINGS register.
> 
> Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
> ---
>  arch/arm/mach-at91/include/mach/at91sam9_smc.h | 31 +++++++++++++++++++++++++-
>  arch/arm/mach-at91/sam9_smc.c                  | 19 ++++++++++++++++
>  2 files changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
> index d5cf5f7..6412664 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
> @@ -43,6 +43,16 @@ struct sam9_smc_config {
>  	/* Mode register */
>  	u32 mode;
>  	u8 tdf_cycles:4;
> +
> +	/* Timings register */
> +	u8 tclr;
> +	u8 tadl;
> +	u8 tar;
> +	u8 ocms;
> +	u8 trr;
> +	u8 twb;
> +	u8 rbnsel;
> +	u8 nfsel;
>  };
>  
>  extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
> @@ -77,7 +87,25 @@ extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
>  #define		AT91_SMC_NRDCYCLE	(0x1ff << 16)			/* Total Read Cycle Length */
>  #define			AT91_SMC_NRDCYCLE_(x)	((x) << 16)
>  
> -#define AT91_SMC_MODE		0x0c				/* Mode Register for CS n */
> +#define AT91_SMC_TIMINGS	0x0c				/* Timings register for CS n */
> +#define		AT91_SMC_TCLR		(0x0f  <<  0)			/* CLE to REN Low Delay */
> +#define			AT91_SMC_TCLR_(x)	((x) << 0)
> +#define		AT91_SMC_TADL		(0x0f  <<  4)			/* ALE to Data Start */
> +#define			AT91_SMC_TADL_(x)	((x) << 4)
> +#define		AT91_SMC_TAR		(0x0f  <<  8)			/* ALE to REN Low Delay */
> +#define			AT91_SMC_TAR_(x)	((x) << 8)
> +#define		AT91_SMC_OCMS		(0x1   << 12)			/* Off Chip Memory Scrambling Enable */
> +#define			AT91_SMC_OCMS_(x)	((x) << 12)
> +#define		AT91_SMC_TRR		(0x0f  << 16)			/* Ready to REN Low Delay */
> +#define			AT91_SMC_TRR_(x)        ((x) << 16)
> +#define		AT91_SMC_TWB		(0x0f  << 24)			/* WEN High to REN to Busy */
> +#define			AT91_SMC_TWB_(x)	((x) << 24)
> +#define		AT91_SMC_RBNSEL		(0x07  << 28)			/* Ready/Busy Line Selection */
> +#define			AT91_SMC_RBNSEL_(x)	((x) << 28)
> +#define		AT91_SMC_NFSEL		(0x01  << 31)			/* Nand Flash Selection */
> +#define			AT91_SMC_NFSEL_(x)	((x) << 31)
> +
> +#define AT91_SMC_MODE		((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? 0x10 : 0x0c)				/* Mode Register for CS n */
>  #define		AT91_SMC_READMODE	(1 <<  0)			/* Read Mode */
>  #define		AT91_SMC_WRITEMODE	(1 <<  1)			/* Write Mode */
>  #define		AT91_SMC_EXNWMODE	(3 <<  4)			/* NWAIT Mode */
> @@ -101,4 +129,5 @@ extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
>  #define			AT91_SMC_PS_16			(2 << 28)
>  #define			AT91_SMC_PS_32			(3 << 28)
>  
> +
>  #endif

This hunk shouldn't be here.

> diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
> index c7bfdfd..89f73ef 100644
> --- a/arch/arm/mach-at91/sam9_smc.c
> +++ b/arch/arm/mach-at91/sam9_smc.c
> @@ -30,6 +30,20 @@ static void sam9_smc_cs_write_mode(void __iomem *base,
>  		   base + AT91_SMC_MODE);
>  }
>  
> +static void sam9_smc_cs_write_timings(void __iomem *base,
> +					struct sam9_smc_config *config)
> +{
> +	__raw_writel(AT91_SMC_TCLR_(config->tclr)
> +                   | AT91_SMC_TADL_(config->tadl)
> +                   | AT91_SMC_TAR_(config->tar)
> +                   | AT91_SMC_OCMS_(config->ocms)
> +                   | AT91_SMC_TRR_(config->trr)
> +                   | AT91_SMC_TWB_(config->twb)
> +                   | AT91_SMC_RBNSEL_(config->rbnsel)
> +                   | AT91_SMC_NFSEL_(config->nfsel),
> +		   base + AT91_SMC_TIMINGS);
> +}
> +
>  void sam9_smc_write_mode(int id, int cs,
>  					struct sam9_smc_config *config)
>  {
> @@ -61,6 +75,11 @@ static void sam9_smc_cs_configure(void __iomem *base,
>  
>  	/* Mode register */
>  	sam9_smc_cs_write_mode(base, config);
> +
> +	/* Timings register */
> +	if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
> +		sam9_smc_cs_write_timings(base, config);
> +	}

I would pretty much prefer a

sama5d3_smc_cs_configure(int id, int cs, struct sama5d3_smc_config *config)

function so that the older SoCs do not have the overhead which the new
SoC requires.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH 2/2] sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot
       [not found] <1405959207-21839-1-git-send-email-matteo.fortini@gmail.com>
@ 2014-07-21 16:13 ` Matteo Fortini
  0 siblings, 0 replies; 5+ messages in thread
From: Matteo Fortini @ 2014-07-21 16:13 UTC (permalink / raw)
  To: barebox

The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization

Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
---
 arch/arm/boards/sama5d3xek/init.c | 29 +++++++++++++++++++----------
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c
index e078642..743197f 100644
--- a/arch/arm/boards/sama5d3xek/init.c
+++ b/arch/arm/boards/sama5d3xek/init.c
@@ -72,21 +72,30 @@ static struct atmel_nand_data nand_pdata = {
 };
 
 static struct sam9_smc_config cm_nand_smc_config = {
-	.ncs_read_setup		= 0,
-	.nrd_setup		= 1,
-	.ncs_write_setup	= 0,
-	.nwe_setup		= 1,
+	.ncs_read_setup		= 1,
+	.nrd_setup		= 2,
+	.ncs_write_setup	= 1,
+	.nwe_setup		= 2,
 
-	.ncs_read_pulse		= 6,
-	.nrd_pulse		= 4,
+	.ncs_read_pulse		= 5,
+	.nrd_pulse		= 3,
 	.ncs_write_pulse	= 5,
 	.nwe_pulse		= 3,
 
-	.read_cycle		= 6,
-	.write_cycle		= 5,
+	.read_cycle		= 8,
+	.write_cycle		= 8,
 
 	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-	.tdf_cycles		= 1,
+	.tdf_cycles		= 3,
+
+	.tclr			= 3,
+	.tadl			= 10,
+	.tar			= 3,
+	.ocms			= 0,
+	.trr			= 4,
+	.twb			= 5,
+	.rbnsel			= 3,
+	.nfsel			= 1
 };
 
 static void ek_add_device_nand(void)
@@ -102,7 +111,7 @@ static void ek_add_device_nand(void)
 		cm_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
 	/* configure chip-select 3 (NAND) */
-	sam9_smc_configure(0, 3, &cm_nand_smc_config);
+	sama5_smc_configure(0, 3, &cm_nand_smc_config);
 
 	at91_add_device_nand(&nand_pdata);
 }
-- 
2.0.1


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^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH 2/2] sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot
       [not found] <1403609192-5862-1-git-send-email-matteo.fortini@gmail.com>
@ 2014-06-24 11:26 ` Matteo Fortini
  0 siblings, 0 replies; 5+ messages in thread
From: Matteo Fortini @ 2014-06-24 11:26 UTC (permalink / raw)
  To: barebox

The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization

Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
---
 arch/arm/boards/sama5d3xek/init.c | 31 +++++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c
index e078642..06e354c 100644
--- a/arch/arm/boards/sama5d3xek/init.c
+++ b/arch/arm/boards/sama5d3xek/init.c
@@ -72,21 +72,32 @@ static struct atmel_nand_data nand_pdata = {
 };
 
 static struct sam9_smc_config cm_nand_smc_config = {
-	.ncs_read_setup		= 0,
-	.nrd_setup		= 1,
-	.ncs_write_setup	= 0,
-	.nwe_setup		= 1,
+	.ncs_read_setup		= 1,
+	.nrd_setup		= 2,
+	.ncs_write_setup	= 1,
+	.nwe_setup		= 2,
 
-	.ncs_read_pulse		= 6,
-	.nrd_pulse		= 4,
+	.ncs_read_pulse		= 5,
+	.nrd_pulse		= 3,
 	.ncs_write_pulse	= 5,
 	.nwe_pulse		= 3,
 
-	.read_cycle		= 6,
-	.write_cycle		= 5,
+	.read_cycle		= 8,
+	.write_cycle		= 8,
 
 	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-	.tdf_cycles		= 1,
+	.tdf_cycles		= 3,
+};
+
+static struct sam9_smc_sama5d3_extra_config cm_nand_smc_sama5d_extra_config = {
+	.tclr			= 3,
+	.tadl			= 10,
+	.tar			= 3,
+	.ocms			= 0,
+	.trr			= 4,
+	.twb			= 5,
+	.rbnsel			= 3,
+	.nfsel			= 1
 };
 
 static void ek_add_device_nand(void)
@@ -102,7 +113,7 @@ static void ek_add_device_nand(void)
 		cm_nand_smc_config.mode |= AT91_SMC_DBW_8;
 
 	/* configure chip-select 3 (NAND) */
-	sam9_smc_configure(0, 3, &cm_nand_smc_config);
+	sam9_smc_sama5d3_configure(0, 3, &cm_nand_smc_config, &cm_nand_smc_sama5d_extra_config);
 
 	at91_add_device_nand(&nand_pdata);
 }
-- 
2.0.0


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     [not found] <1402045936-18733-1-git-send-email-matteo.fortini@gmail.com>
2014-06-06  9:12 ` [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register Matteo Fortini
2014-06-10  6:33   ` Sascha Hauer
2014-06-06  9:12 ` [PATCH 2/2] sama5d3x: HSMC NAND initialize TIMINGS and import values from U-Boot Matteo Fortini
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