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From: Matteo Fortini <matteo.fortini@gmail.com>
Date: Tue, 24 Jun 2014 13:26:30 +0200
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Subject: [PATCH V2] SAMA5D3 SMC: Fix CS offset and add TIMINGS register
To: barebox@lists.infradead.org

As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
MODE register has offset 0x10 while at offset 0x0C there is
a TIMINGS register.
This patch series adds the register and configures it for 
sama5d3xek using timings from U-Boot

[PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS
[PATCH 2/2] sama5d3x: HSMC NAND initialize TIMINGS and import values

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