From: Stephano Cetola <stephano@cetola.net>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>,
Sascha Hauer <s.hauer@pengutronix.de>,
"open list:BAREBOX" <barebox@lists.infradead.org>
Subject: Re: [PATCH] ARM: mmu: fix flush_cacheable_pages off-by-one touching guard page
Date: Mon, 24 Aug 2026 08:30:58 -0700 [thread overview]
Message-ID: <bc3c0e72-788c-41e2-a3c1-6c1b09ae3e04@cetola.net> (raw)
In-Reply-To: <66e33b76-4121-4c1c-8a2d-8b6d74e3d3d4@pengutronix.de>
On 8/24/26 6:27 AM, Ahmad Fatoum wrote:
> Hello Stephano,
>
> Thanks for your patch!
Thank you for encouraging me to upstream. :)
>
> I agree there is a bug here, but making flush_end exclusive doesn't
> sound like the best remedy to me, exactly because these + 1's and - 1's
> are so error-prone.
Ah okay, this makes sense now.
>
> Also it seems the code has problems if a cached region reaches the end
> of address space, which can happen on some 32-bit ARM SoCs, like the i.MX6Q.
>
> I am working on a revised patch that I will share within the week.
>
Excellent. I will test your fix on the Radxa CM5 RK3588S2. Let me know
if there's anything else I can do to help here.
Cheers,
Stephano
prev parent reply other threads:[~2026-08-24 15:32 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-22 14:06 Stephano Cetola
2026-08-24 13:27 ` Ahmad Fatoum
2026-08-24 15:30 ` Stephano Cetola [this message]
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