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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: "barebox@lists.infradead.org" <barebox@lists.infradead.org>
Subject: Re: [PATCH 2/2] mci: stm32_sdmmc2: enable eMMC 52MHz DDR mode
Date: Thu, 23 Nov 2023 11:54:04 +0100	[thread overview]
Message-ID: <bdad3dff-a8d8-b9a3-ccba-0d6711362ce0@pengutronix.de> (raw)
In-Reply-To: <20231123103808.432548-2-a.fatoum@pengutronix.de>

On 23.11.23 11:38, Ahmad Fatoum wrote:
> Dual data rate can be enabled on STM32 SDMMC2 host by toggling a bit in
> the CLKRC register and avoiding clock bypass. Let's do that for a nice
> boost in throughput. Before:
> 
>   barebox@STM32MP157C-ED1:/ time cp /dev/mmc0.data /tmp
>   time: 2684ms
> 
> After:
> 
>   barebox@STM32MP157C-ED1:/ time cp /dev/mmc1.data /tmp
>   time: 1624ms

while reading a 100 MiB partition, i.e. 37.2 MiB/s -> 61.5 MiB/s.

> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  drivers/mci/stm32_sdmmc2.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mci/stm32_sdmmc2.c b/drivers/mci/stm32_sdmmc2.c
> index 90e969a867e6..1bfef1ccf0eb 100644
> --- a/drivers/mci/stm32_sdmmc2.c
> +++ b/drivers/mci/stm32_sdmmc2.c
> @@ -538,11 +538,14 @@ static void stm32_sdmmc2_set_ios(struct mci_host *mci, struct mci_ios *ios)
>  	struct stm32_sdmmc2_priv *priv = to_mci_host(mci);
>  	u32 desired = mci->clock;
>  	u32 sys_clock = clk_get_rate(priv->clk);
> -	u32 clk = 0;
> +	u32 clk = 0, ddr = 0;
>  
>  	dev_dbg(priv->dev, "%s: bus_width = %d, clock = %d\n", __func__,
>  		mci->bus_width, mci->clock);
>  
> +	if (mci_timing_is_ddr(ios->timing))
> +		ddr = SDMMC_CLKCR_DDR;
> +
>  	if (mci->clock)
>  		stm32_sdmmc2_pwron(priv);
>  	else
> @@ -555,13 +558,15 @@ static void stm32_sdmmc2_set_ios(struct mci_host *mci, struct mci_ios *ios)
>  	 * clk_div > 0 and NEGEDGE = 1 => command and data generated on
>  	 * SDMMCCLK falling edge
>  	 */
> -	if (desired && (sys_clock > desired ||
> +	if (desired && (sys_clock > desired || ddr ||
>  			IS_RISING_EDGE(priv->clk_reg_msk))) {
>  		clk = DIV_ROUND_UP(sys_clock, 2 * desired);
>  		if (clk > SDMMC_CLKCR_CLKDIV_MAX)
>  			clk = SDMMC_CLKCR_CLKDIV_MAX;
>  	}
>  
> +	clk |= ddr;
> +
>  	if (mci->bus_width == MMC_BUS_WIDTH_4)
>  		clk |= SDMMC_CLKCR_WIDBUS_4;
>  	if (mci->bus_width == MMC_BUS_WIDTH_8)
> @@ -624,6 +629,11 @@ static int stm32_sdmmc2_probe(struct amba_device *adev,
>  	if (mci->f_max >= 52000000)
>  		mci->host_caps |= MMC_CAP_MMC_HIGHSPEED_52MHZ;
>  
> +	if (of_property_read_bool(np, "mmc-ddr-3_3v"))
> +		mci->host_caps |= MMC_CAP_MMC_3_3V_DDR;
> +	if (of_property_read_bool(np, "mmc-ddr-1_8v"))
> +		mci->host_caps |= MMC_CAP_MMC_1_8V_DDR;
> +
>  	return mci_register(&priv->mci);
>  
>  priv_free:

-- 
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  reply	other threads:[~2023-11-23 10:55 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-23 10:38 [PATCH 1/2] mci: core: check for both 3.3v and 1.8v DDR support Ahmad Fatoum
2023-11-23 10:38 ` [PATCH 2/2] mci: stm32_sdmmc2: enable eMMC 52MHz DDR mode Ahmad Fatoum
2023-11-23 10:54   ` Ahmad Fatoum [this message]
2023-11-23 14:54 ` [PATCH 1/2] mci: core: check for both 3.3v and 1.8v DDR support Sascha Hauer

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