* [PATCH] ARM: vector_table: Fix creation of second level page table
@ 2016-08-24 12:23 Sascha Hauer
2016-08-24 16:07 ` Andrey Smirnov
2016-08-25 20:50 ` Peter Kardos
0 siblings, 2 replies; 4+ messages in thread
From: Sascha Hauer @ 2016-08-24 12:23 UTC (permalink / raw)
To: Barebox List; +Cc: Peter Kardos
The second level page tables can only start at a 1MiB section boundary,
so instead of calling arm_create_pte() with the high vector address
(which is 0xffff0000, not 1MiB aligned) we have to call it with
0xfff00000 to correctly create a second level page table. The vectors
themselves worked as expected with the old value, but the memory around
it did not do a 1:1 mapping anymore. This breaks SoCs which have
peripherals in that area, for example Atmel SoCs like the AT91RM9200.
Fixes: f6b77fe9: ARM: Rework vector table setup
Reported-by: Peter Kardos <kardos.peter.sk@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index a31bce4..2b70866 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -307,7 +307,7 @@ static void create_vector_table(unsigned long adr)
vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n",
vectors, adr);
- exc = arm_create_pte(adr);
+ exc = arm_create_pte(adr & ~(SZ_1M - 1));
idx = (adr & (SZ_1M - 1)) >> PAGE_SHIFT;
exc[idx] = (u32)vectors | PTE_TYPE_SMALL | pte_flags_cached;
}
--
2.8.1
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] ARM: vector_table: Fix creation of second level page table
2016-08-24 12:23 [PATCH] ARM: vector_table: Fix creation of second level page table Sascha Hauer
@ 2016-08-24 16:07 ` Andrey Smirnov
2016-08-25 6:37 ` Sascha Hauer
2016-08-25 20:50 ` Peter Kardos
1 sibling, 1 reply; 4+ messages in thread
From: Andrey Smirnov @ 2016-08-24 16:07 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List, Peter Kardos
On Wed, Aug 24, 2016 at 5:23 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> The second level page tables can only start at a 1MiB section boundary,
> so instead of calling arm_create_pte() with the high vector address
> (which is 0xffff0000, not 1MiB aligned) we have to call it with
> 0xfff00000 to correctly create a second level page table. The vectors
> themselves worked as expected with the old value, but the memory around
> it did not do a 1:1 mapping anymore. This breaks SoCs which have
> peripherals in that area, for example Atmel SoCs like the AT91RM9200.
>
Would you mind re-wording it as something to the effect of: "...
mapping anymore, breaking SoCs which also have peripherals in that
area..."? The original sentence structure, to me, reads as if this
patch/commit introduces a change that breaks Atmel SoCs.
> Fixes: f6b77fe9: ARM: Rework vector table setup
>
> Reported-by: Peter Kardos <kardos.peter.sk@gmail.com>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/cpu/mmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> index a31bce4..2b70866 100644
> --- a/arch/arm/cpu/mmu.c
> +++ b/arch/arm/cpu/mmu.c
> @@ -307,7 +307,7 @@ static void create_vector_table(unsigned long adr)
> vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
> pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n",
> vectors, adr);
> - exc = arm_create_pte(adr);
> + exc = arm_create_pte(adr & ~(SZ_1M - 1));
ALIGN_DOWN(adr, SZ_1M) ?
Thanks,
Andrey Smirnov
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* Re: [PATCH] ARM: vector_table: Fix creation of second level page table
2016-08-24 16:07 ` Andrey Smirnov
@ 2016-08-25 6:37 ` Sascha Hauer
0 siblings, 0 replies; 4+ messages in thread
From: Sascha Hauer @ 2016-08-25 6:37 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: Barebox List, Peter Kardos
On Wed, Aug 24, 2016 at 09:07:22AM -0700, Andrey Smirnov wrote:
> On Wed, Aug 24, 2016 at 5:23 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > The second level page tables can only start at a 1MiB section boundary,
> > so instead of calling arm_create_pte() with the high vector address
> > (which is 0xffff0000, not 1MiB aligned) we have to call it with
> > 0xfff00000 to correctly create a second level page table. The vectors
> > themselves worked as expected with the old value, but the memory around
> > it did not do a 1:1 mapping anymore. This breaks SoCs which have
> > peripherals in that area, for example Atmel SoCs like the AT91RM9200.
> >
>
> Would you mind re-wording it as something to the effect of: "...
> mapping anymore, breaking SoCs which also have peripherals in that
> area..."? The original sentence structure, to me, reads as if this
> patch/commit introduces a change that breaks Atmel SoCs.
Sure.
>
> > Fixes: f6b77fe9: ARM: Rework vector table setup
> >
> > Reported-by: Peter Kardos <kardos.peter.sk@gmail.com>
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > arch/arm/cpu/mmu.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> > index a31bce4..2b70866 100644
> > --- a/arch/arm/cpu/mmu.c
> > +++ b/arch/arm/cpu/mmu.c
> > @@ -307,7 +307,7 @@ static void create_vector_table(unsigned long adr)
> > vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
> > pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n",
> > vectors, adr);
> > - exc = arm_create_pte(adr);
> > + exc = arm_create_pte(adr & ~(SZ_1M - 1));
>
> ALIGN_DOWN(adr, SZ_1M) ?
Yes, that's better. I just sent an updated version.
Sascha
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] ARM: vector_table: Fix creation of second level page table
2016-08-24 12:23 [PATCH] ARM: vector_table: Fix creation of second level page table Sascha Hauer
2016-08-24 16:07 ` Andrey Smirnov
@ 2016-08-25 20:50 ` Peter Kardos
1 sibling, 0 replies; 4+ messages in thread
From: Peter Kardos @ 2016-08-25 20:50 UTC (permalink / raw)
To: Sascha Hauer, Barebox List
Tested with my AT91RM9200 system, v2016.08 + patch; The system
starts/boots as expected.
If no one objects, we can consider this issue closed/fixed.
Peter
On 8/24/2016 2:23 PM, Sascha Hauer wrote:
> The second level page tables can only start at a 1MiB section boundary,
> so instead of calling arm_create_pte() with the high vector address
> (which is 0xffff0000, not 1MiB aligned) we have to call it with
> 0xfff00000 to correctly create a second level page table. The vectors
> themselves worked as expected with the old value, but the memory around
> it did not do a 1:1 mapping anymore. This breaks SoCs which have
> peripherals in that area, for example Atmel SoCs like the AT91RM9200.
>
> Fixes: f6b77fe9: ARM: Rework vector table setup
>
> Reported-by: Peter Kardos <kardos.peter.sk@gmail.com>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> arch/arm/cpu/mmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
> index a31bce4..2b70866 100644
> --- a/arch/arm/cpu/mmu.c
> +++ b/arch/arm/cpu/mmu.c
> @@ -307,7 +307,7 @@ static void create_vector_table(unsigned long adr)
> vectors = xmemalign(PAGE_SIZE, PAGE_SIZE);
> pr_debug("Creating vector table, virt = 0x%p, phys = 0x%08lx\n",
> vectors, adr);
> - exc = arm_create_pte(adr);
> + exc = arm_create_pte(adr & ~(SZ_1M - 1));
> idx = (adr & (SZ_1M - 1)) >> PAGE_SHIFT;
> exc[idx] = (u32)vectors | PTE_TYPE_SMALL | pte_flags_cached;
> }
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2016-08-24 16:07 ` Andrey Smirnov
2016-08-25 6:37 ` Sascha Hauer
2016-08-25 20:50 ` Peter Kardos
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