* RK3568 some question
@ 2023-10-13 8:12 Alexander Shiyan
2023-10-13 10:37 ` Sascha Hauer
2023-10-13 10:53 ` Lucas Stach
0 siblings, 2 replies; 3+ messages in thread
From: Alexander Shiyan @ 2023-10-13 8:12 UTC (permalink / raw)
To: Barebox List
Hello.
I'm trying to run PCI-e 2.0 on an RK3568 processor. The driver loads
OK and does not detect anyone on the bus except itself.
In the kernel, everything works as it should and connected devices are
visible on the bus (in my case, I use Intel AX200 and MediaTek MT7921e
Wi-Fi modules).
Enabling PCI debugging produces these messages:
pbar0 set bad mask
pbar1 set bad mask
Has anyone run PCI on this CPU?
I'm not too familiar with the PCI subsystem, but after briefly looking
at the code,
I saw in the setup_device() function the line:
pci_write_config_dword(dev, pci_base_address_0, 0xfffffffe);
On Linux and u-boot this value is ~0.
The question is, are we doing the right thing here?
And the question is not related to the PCI:
rk3568_lowlevel_init() does not call arm_cpu_lowlevel_init(). Is this OK?
Thanks!
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: RK3568 some question
2023-10-13 8:12 RK3568 some question Alexander Shiyan
@ 2023-10-13 10:37 ` Sascha Hauer
2023-10-13 10:53 ` Lucas Stach
1 sibling, 0 replies; 3+ messages in thread
From: Sascha Hauer @ 2023-10-13 10:37 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: Barebox List
On Fri, Oct 13, 2023 at 11:12:49AM +0300, Alexander Shiyan wrote:
> Hello.
>
> I'm trying to run PCI-e 2.0 on an RK3568 processor. The driver loads
> OK and does not detect anyone on the bus except itself.
> In the kernel, everything works as it should and connected devices are
> visible on the bus (in my case, I use Intel AX200 and MediaTek MT7921e
> Wi-Fi modules).
> Enabling PCI debugging produces these messages:
> pbar0 set bad mask
> pbar1 set bad mask
> Has anyone run PCI on this CPU?
I've added the Rockchip PCIe driver for the RK3588 and tested it working
there. I never used it on the RK3568 due to the lack of hardware.
I don't have the Rock5b board handy at the moment, but maybe I can have
a look the next days what the register reads there.
>
> I'm not too familiar with the PCI subsystem, but after briefly looking
> at the code,
> I saw in the setup_device() function the line:
> pci_write_config_dword(dev, pci_base_address_0, 0xfffffffe);
> On Linux and u-boot this value is ~0.
> The question is, are we doing the right thing here?
I don't know. Where is the corresponding place in Linux?
>
> And the question is not related to the PCI:
> rk3568_lowlevel_init() does not call arm_cpu_lowlevel_init(). Is this OK?
It should be called once on each board and rk3568_lowlevel_init() seems
like a good place for it.
Sascha
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: RK3568 some question
2023-10-13 8:12 RK3568 some question Alexander Shiyan
2023-10-13 10:37 ` Sascha Hauer
@ 2023-10-13 10:53 ` Lucas Stach
1 sibling, 0 replies; 3+ messages in thread
From: Lucas Stach @ 2023-10-13 10:53 UTC (permalink / raw)
To: Alexander Shiyan, Barebox List
Am Freitag, dem 13.10.2023 um 11:12 +0300 schrieb Alexander Shiyan:
> Hello.
>
[...]
> I'm not too familiar with the PCI subsystem, but after briefly looking
> at the code,
> I saw in the setup_device() function the line:
> pci_write_config_dword(dev, pci_base_address_0, 0xfffffffe);
> On Linux and u-boot this value is ~0.
> The question is, are we doing the right thing here?
We can change this to be consistent with Linux, but in practice it
probably won't matter, as this bit signifies if the BAR is a memory or
IO resource and is hardcoded in any real device and not dependent on
writing ones to the BAR register to return the correct value.
Regards,
Lucas
^ permalink raw reply [flat|nested] 3+ messages in thread
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