* [DistroKit] [PATCH v2 3/5] v8a: kernel: import imx8mp-frdm device tree
2026-03-16 10:19 [DistroKit] [PATCH v2 0/5] RFC: add support for imx8mp-frdm board Fabian Pfitzner
2026-03-16 10:19 ` [DistroKit] [PATCH v2 1/5] v8a: barebox: enable " Fabian Pfitzner
2026-03-16 10:19 ` [DistroKit] [PATCH v2 2/5] v8a: kernel: add imx8mp-frdm dts Fabian Pfitzner
@ 2026-03-16 10:19 ` Fabian Pfitzner
2026-03-16 10:19 ` [DistroKit] [PATCH v2 4/5] v8a: add imx8mp-frdm image Fabian Pfitzner
2026-03-16 10:19 ` [DistroKit] [PATCH v2 5/5] doc: add imx8mp-frdm Fabian Pfitzner
4 siblings, 0 replies; 6+ messages in thread
From: Fabian Pfitzner @ 2026-03-16 10:19 UTC (permalink / raw)
To: distrokit; +Cc: Fabian Pfitzner
As the imx8mp-frdm device tree is not yet upstream in the Linux kernel,
import it here [1]. Furthermore add downstream changes from NXP [2] that add
functionality for
- WiFi
- HDMI
- Ethernet
- USB
- SD Card
[1] https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/commit/?h=imx/dt64&id=bb5b318f11e6f41c8cbb51848555f58b9ef175e6
[2] git@github.com:nxp-imx/linux-imx.git
Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de>
---
...ts-add-support-for-NXP-i.MX8MP-FRDM-board.patch | 413 ++++++++++++++++++
...mx8mp-frdm-add-sd-ethernet-wifi-usb-and-h.patch | 485 +++++++++++++++++++++
configs/platform-v8a/patches/linux-6.18/series | 5 +
3 files changed, 903 insertions(+)
diff --git a/configs/platform-v8a/patches/linux-6.18/0001-arm64-dts-add-support-for-NXP-i.MX8MP-FRDM-board.patch b/configs/platform-v8a/patches/linux-6.18/0001-arm64-dts-add-support-for-NXP-i.MX8MP-FRDM-board.patch
new file mode 100644
index 0000000000000000000000000000000000000000..74731bcc0533b77e9a9d38265ae2292f7dfb803a
--- /dev/null
+++ b/configs/platform-v8a/patches/linux-6.18/0001-arm64-dts-add-support-for-NXP-i.MX8MP-FRDM-board.patch
@@ -0,0 +1,413 @@
+From bb5b318f11e6f41c8cbb51848555f58b9ef175e6 Mon Sep 17 00:00:00 2001
+From: Rogerio Pimentel <rpimentel.silva@gmail.com>
+Date: Sun, 23 Nov 2025 13:14:44 -0500
+Subject: [PATCH] arm64: dts: add support for NXP i.MX8MP FRDM board
+
+The FRDM-i.MX8MP is an NXP development platform based on the i.MX8M Plus
+SoC, featuring a quad Cortex-A53, Cortex-M7 co-processor, 4GB LPDDR4,
+32GB eMMC, Wi-Fi 6/Bluetooth 5.4/802.15.4 tri-radio, Ethernet, HDMI/MIPI
+display interfaces, camera connectors, and standard expansion headers.
+
+Based on the device tree found in the NXP repository at github
+https://github.com/nxp-imx-support/meta-imx-frdm and on imx8mp-evk
+board kernel mainline device tree.
+
+This is a basic device tree supporting:
+
+ - Quad Cortex-A53
+ - 4GB LPDDR4 DRAM
+ - PCA9450C PMIC with regulators
+ - Two NXP PCAL6416 GPIO expanders
+ - RGB LEDs via GPIO expander
+ - I2C1, I2C2, I2C3 controllers
+ - UART2 (console) and UART3 (with RTS/CTS)
+ - USDHC3 (8-bit eMMC)
+ - SNVS power key (onboard power button)
+
+Co-developed-by: Xiaofeng Wei <xiaofeng.wei@nxp.com>
+Signed-off-by: Xiaofeng Wei <xiaofeng.wei@nxp.com>
+Signed-off-by: Rogerio Pimentel <rpimentel.silva@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/Makefile | 1 +
+ arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 355 ++++++++++++++++++
+ 2 files changed, 356 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
+
+diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
+index db3d56fc7db6c..862788fb3ea48 100644
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -214,6 +214,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
++dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
+new file mode 100644
+index 0000000000000..55690f5e53d7e
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
+@@ -0,0 +1,355 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2019 NXP
++ */
++
++/dts-v1/;
++
++#include "imx8mp.dtsi"
++
++/ {
++ model = "NXP i.MX8MPlus FRDM board";
++ compatible = "fsl,imx8mp-frdm", "fsl,imx8mp";
++
++ chosen {
++ stdout-path = &uart2;
++ };
++
++ gpio-leds {
++ compatible = "gpio-leds";
++
++ led-0 {
++ label = "red";
++ gpios = <&pcal6416_0 13 GPIO_ACTIVE_HIGH>;
++ default-state = "off";
++ };
++
++ led-1 {
++ label = "green";
++ gpios = <&pcal6416_0 14 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ };
++
++ led-2 {
++ label = "blue";
++ gpios = <&pcal6416_0 15 GPIO_ACTIVE_HIGH>;
++ default-state = "off";
++ };
++ };
++
++ memory@40000000 {
++ device_type = "memory";
++ reg = <0x0 0x40000000 0 0xc0000000>,
++ <0x1 0x00000000 0 0x40000000>;
++ };
++};
++
++&A53_0 {
++ cpu-supply = <®_arm>;
++};
++
++&A53_1 {
++ cpu-supply = <®_arm>;
++};
++
++&A53_2 {
++ cpu-supply = <®_arm>;
++};
++
++&A53_3 {
++ cpu-supply = <®_arm>;
++};
++
++&i2c1 {
++ clock-frequency = <400000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "okay";
++
++ pmic@25 {
++ compatible = "nxp,pca9450c";
++ reg = <0x25>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pmic>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
++
++ regulators {
++ BUCK1 {
++ regulator-name = "BUCK1";
++ regulator-min-microvolt = <720000>;
++ regulator-max-microvolt = <1000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <3125>;
++ };
++
++ reg_arm: BUCK2 {
++ regulator-name = "BUCK2";
++ regulator-min-microvolt = <720000>;
++ regulator-max-microvolt = <1025000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <3125>;
++ nxp,dvs-run-voltage = <950000>;
++ nxp,dvs-standby-voltage = <850000>;
++ };
++
++ BUCK4 {
++ regulator-name = "BUCK4";
++ regulator-min-microvolt = <3000000>;
++ regulator-max-microvolt = <3600000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ reg_buck5: BUCK5 {
++ regulator-name = "BUCK5";
++ regulator-min-microvolt = <1650000>;
++ regulator-max-microvolt = <1950000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ BUCK6 {
++ regulator-name = "BUCK6";
++ regulator-min-microvolt = <1045000>;
++ regulator-max-microvolt = <1155000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ LDO1 {
++ regulator-name = "LDO1";
++ regulator-min-microvolt = <1650000>;
++ regulator-max-microvolt = <1950000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ LDO3 {
++ regulator-name = "LDO3";
++ regulator-min-microvolt = <1710000>;
++ regulator-max-microvolt = <1890000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ LDO5 {
++ regulator-name = "LDO5";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++ };
++ };
++
++ pcal6416_0: gpio@20 {
++ compatible = "nxp,pcal6416";
++ reg = <0x20>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcal6416_0_int>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
++ gpio-line-names = "CSI1_nRST",
++ "CSI2_nRST",
++ "DSI_CTP_RST",
++ "EXT_PWREN1",
++ "CAN_STBY",
++ "EXP_P0_5",
++ "EXP_P0_6",
++ "P0_7",
++ "LVDS0_BLT_EN",
++ "LVDS1_BLT_EN",
++ "LVDS0_CTP_RST",
++ "LVDS1_CTP_RST",
++ "SPK_PWREN",
++ "RLED_GPIO",
++ "GLED_GPIO",
++ "BLED_GPIO";
++ };
++
++ pcal6416_1: gpio@21 {
++ compatible = "nxp,pcal6416";
++ reg = <0x21>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcal6416_1_int>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ gpio-line-names = "P0_0",
++ "P0_1",
++ "AUD_nINT",
++ "RTC_nINTA",
++ "USB1_SS_SEL",
++ "USB2_PWR_EN",
++ "SPI_EXP_SEL",
++ "P0_7",
++ "W2_HOST_WAKE_SD_3V3",
++ "W2_HOST_WAKE_BT_3V3",
++ "EXP_WIFI_BT_PDN_3V3",
++ "EXP_BT_RST_3V3",
++ "W2_RST_IND_3V3",
++ "SPI_nINT_3V3",
++ "KEYM_PCIE_nWAKE",
++ "P1_7";
++ };
++};
++
++&i2c2 {
++ clock-frequency = <400000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++};
++
++&i2c3 {
++ clock-frequency = <400000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ status = "okay";
++};
++
++&snvs_pwrkey {
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2>;
++ status = "okay";
++};
++
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart3>;
++ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
++ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
++ uart-has-rtscts;
++ status = "okay";
++};
++
++&usdhc3 {
++ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
++ assigned-clock-rates = <400000000>;
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
++ bus-width = <8>;
++ non-removable;
++ status = "okay";
++};
++
++&iomuxc {
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
++ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
++ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
++ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
++ >;
++ };
++
++ pinctrl_pmic: pmicgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
++ >;
++ };
++
++ pinctrl_pcal6416_0_int: pcal6416-0-int-grp {
++ fsl,pins = <
++ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x146
++ >;
++ };
++
++ pinctrl_pcal6416_1_int: pcal6416-1-int-grp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x146
++ >;
++ };
++
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
++ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
++ >;
++ };
++
++ pinctrl_uart3: uart3grp {
++ fsl,pins = <
++ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
++ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
++ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
++ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
++ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
++ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
++ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
++ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
++ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
++ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
++ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
++ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
++ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
++ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
++ >;
++ };
++
++ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
++ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
++ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
++ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
++ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
++ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
++ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
++ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
++ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
++ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
++ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
++ >;
++ };
++
++ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
++ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
++ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
++ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
++ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
++ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
++ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
++ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
++ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
++ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
++ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
++ >;
++ };
++};
+--
+2.47.3
+
diff --git a/configs/platform-v8a/patches/linux-6.18/0002-arm64-dts-imx8mp-frdm-add-sd-ethernet-wifi-usb-and-h.patch b/configs/platform-v8a/patches/linux-6.18/0002-arm64-dts-imx8mp-frdm-add-sd-ethernet-wifi-usb-and-h.patch
new file mode 100644
index 0000000000000000000000000000000000000000..e5afd9c7b371c456394b48a8466f29d2f88775c3
--- /dev/null
+++ b/configs/platform-v8a/patches/linux-6.18/0002-arm64-dts-imx8mp-frdm-add-sd-ethernet-wifi-usb-and-h.patch
@@ -0,0 +1,485 @@
+From ffd1982a4f4833d18690d02b836ccf1e1a78a047 Mon Sep 17 00:00:00 2001
+From: Fabian Pfitzner <f.pfitzner@pengutronix.de>
+Date: Wed, 7 Jan 2026 16:58:37 +0100
+Subject: [PATCH] arm64: dts: imx8mp-frdm: add sd, ethernet, wifi, usb and hdmi
+ support
+
+Add support for the following new features:
+
+- SD Card
+- Ethernet (FEC + EQOS)
+- Wifi
+- USB
+- HDMI
+
+The imx8mp-evk dt and the NXP downstream imx8mp-frdm dts were
+taken as a reference.
+
+Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 407 ++++++++++++++++++
+ 1 file changed, 407 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
+index 55690f5e53d7e..c3691887bb845 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
+@@ -42,6 +42,67 @@ memory@40000000 {
+ reg = <0x0 0x40000000 0 0xc0000000>,
+ <0x1 0x00000000 0 0x40000000>;
+ };
++
++ native-hdmi-connector {
++ compatible = "hdmi-connector";
++ label = "HDMI OUT";
++ type = "a";
++
++ port {
++ hdmi_in: endpoint {
++ remote-endpoint = <&hdmi_tx_out>;
++ };
++ };
++ };
++
++ reg_usdhc2_vmmc: regulator-sd {
++ compatible = "regulator-fixed";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
++ regulator-name = "VSD_3V3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ reg_usb_vbus: regulator-vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "USB_VBUS";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&pcal6416_1 5 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ reg_usdhc1_vmmc: regulator-wifi-vmmc {
++ compatible = "regulator-fixed";
++ regulator-name = "WLAN_EN";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&pcal6416_1 10 GPIO_ACTIVE_HIGH>;
++ /*
++ * IW612 wifi chip needs more delay than other wifi chips to complete
++ * the host interface initialization after power up, otherwise the
++ * internal state of IW612 may be unstable, resulting in the failure of
++ * the SDIO3.0 switch voltage.
++ */
++ enable-active-high;
++ startup-delay-us = <20000>;
++ };
++
++ reg_usdhc1_vqmmc: regulator-wifi-vqmmc {
++ compatible = "regulator-fixed";
++ regulator-name = "regulator-wifi-vqmmc";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ enable-active-high;
++ };
++
++ sdio_pwrseq: usdhc1-pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
++ };
+ };
+
+ &A53_0 {
+@@ -60,6 +121,147 @@ &A53_3 {
+ cpu-supply = <®_arm>;
+ };
+
++&eqos {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_eqos>;
++ phy-mode = "rgmii-id";
++ phy-handle = <ðphy0>;
++ snps,force_thresh_dma_mode;
++ snps,mtl-tx-config = <&mtl_tx_setup>;
++ snps,mtl-rx-config = <&mtl_rx_setup>;
++ status = "okay";
++
++ mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethphy0: ethernet-phy@2 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_eqos_phy>;
++ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
++ reset-assert-us = <10000>;
++ reset-deassert-us = <80000>;
++ };
++ };
++
++ mtl_tx_setup: tx-queues-config {
++ snps,tx-queues-to-use = <5>;
++
++ queue0 {
++ snps,dcb-algorithm;
++ snps,priority = <0x1>;
++ };
++
++ queue1 {
++ snps,dcb-algorithm;
++ snps,priority = <0x2>;
++ };
++
++ queue2 {
++ snps,dcb-algorithm;
++ snps,priority = <0x4>;
++ };
++
++ queue3 {
++ snps,dcb-algorithm;
++ snps,priority = <0x8>;
++ };
++
++ queue4 {
++ snps,dcb-algorithm;
++ snps,priority = <0xf0>;
++ };
++ };
++
++ mtl_rx_setup: rx-queues-config {
++ snps,rx-queues-to-use = <5>;
++ snps,rx-sched-sp;
++
++ queue0 {
++ snps,dcb-algorithm;
++ snps,priority = <0x1>;
++ snps,map-to-dma-channel = <0>;
++ };
++
++ queue1 {
++ snps,dcb-algorithm;
++ snps,priority = <0x2>;
++ snps,map-to-dma-channel = <1>;
++ };
++
++ queue2 {
++ snps,dcb-algorithm;
++ snps,priority = <0x4>;
++ snps,map-to-dma-channel = <2>;
++ };
++
++ queue3 {
++ snps,dcb-algorithm;
++ snps,priority = <0x8>;
++ snps,map-to-dma-channel = <3>;
++ };
++
++ queue4 {
++ snps,dcb-algorithm;
++ snps,priority = <0xf0>;
++ snps,map-to-dma-channel = <4>;
++ };
++ };
++};
++
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_fec>;
++ phy-mode = "rgmii-id";
++ phy-handle = <ðphy1>;
++ fsl,magic-packet;
++ status = "okay";
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethphy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_fec_phy>;
++ eee-broken-1000t;
++ reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
++ reset-assert-us = <10000>;
++ reset-deassert-us = <80000>;
++ realtek,aldps-enable;
++ realtek,clkout-disable;
++ };
++ };
++};
++
++
++&hdmi_pvi {
++ status = "okay";
++};
++
++&hdmi_tx {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi>;
++ status = "okay";
++
++ ports {
++ port@1 {
++ hdmi_tx_out: endpoint {
++ remote-endpoint = <&hdmi_in>;
++ };
++ };
++ };
++};
++
++&hdmi_tx_phy {
++ status = "okay";
++};
++
+ &i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+@@ -218,6 +420,32 @@ &i2c3 {
+ status = "okay";
+ };
+
++&lcdif3 {
++ status = "okay";
++};
++
++&usb3_0 {
++ status = "okay";
++};
++
++&usb3_1 {
++ status = "okay";
++};
++
++&usb3_phy0 {
++ status = "okay";
++};
++
++&usb3_phy1 {
++ vbus-supply = <®_usb_vbus>;
++ status = "okay";
++};
++
++&usb_dwc3_1 {
++ dr_mode = "host";
++ status = "okay";
++};
++
+ &snvs_pwrkey {
+ status = "okay";
+ };
+@@ -237,6 +465,36 @@ &uart3 {
+ status = "okay";
+ };
+
++&usdhc1 {
++ assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
++ assigned-clock-rates = <200000000>;
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc1>;
++ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
++ mmc-pwrseq = <&sdio_pwrseq>;
++ vmmc-supply = <®_usdhc1_vmmc>;
++ vqmmc-supply = <®_usdhc1_vqmmc>;
++ bus-width = <4>;
++ non-removable;
++ no-sd;
++ no-mmc;
++ status = "okay";
++};
++
++&usdhc2 {
++ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
++ assigned-clock-rates = <400000000>;
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
++ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
++ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
++ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
++ vmmc-supply = <®_usdhc2_vmmc>;
++ bus-width = <4>;
++ status = "okay";
++};
++
+ &usdhc3 {
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
+@@ -250,6 +508,74 @@ &usdhc3 {
+ };
+
+ &iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++
++ pinctrl_eqos: eqosgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
++ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
++ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
++ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
++ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
++ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
++ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
++ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
++ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
++ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
++ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
++ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
++ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
++ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
++ >;
++ };
++
++ pinctrl_eqos_phy: eqosphygrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
++ >;
++ };
++
++ pinctrl_fec: fecgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
++ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
++ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
++ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
++ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
++ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
++ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
++ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
++ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
++ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
++ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
++ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
++ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
++ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
++ >;
++ };
++
++ pinctrl_fec_phy: fecphygrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
++ >;
++ };
++
++ pinctrl_hdmi: hdmigrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
++ >;
++ };
++
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ /* Pin might be required by multiple drivers
++ * (e. g. HDMI Audio and HDMI TX)
++ */
++ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010
++ >;
++ };
++
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
+@@ -289,6 +615,12 @@ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x146
+ >;
+ };
+
++ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
++ >;
++ };
++
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
+@@ -305,6 +637,81 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
+ >;
+ };
+
++ pinctrl_usdhc1: usdhc1grp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
++ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
++ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
++ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
++ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
++ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
++ >;
++ };
++
++ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
++ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
++ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
++ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
++ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
++ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
++ >;
++ };
++
++ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
++ MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
++ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
++ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
++ MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
++ MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
++ >;
++ };
++
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
++ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
++ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
++ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
++ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
++ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
++ >;
++ };
++
++ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
++ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
++ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
++ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
++ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
++ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
++ >;
++ };
++
++ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
++ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
++ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
++ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
++ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
++ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
++ >;
++ };
++
++ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
++ >;
++ };
++
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+--
+2.47.3
+
diff --git a/configs/platform-v8a/patches/linux-6.18/series b/configs/platform-v8a/patches/linux-6.18/series
new file mode 100644
index 0000000000000000000000000000000000000000..f84c2ad5ac32d398ce62ac5c8948b19ba96249ad
--- /dev/null
+++ b/configs/platform-v8a/patches/linux-6.18/series
@@ -0,0 +1,5 @@
+# generated by git-ptx-patches
+#tag:base --start-number 1
+0001-arm64-dts-add-support-for-NXP-i.MX8MP-FRDM-board.patch
+0002-arm64-dts-imx8mp-frdm-add-sd-ethernet-wifi-usb-and-h.patch
+# 6f01bc63173b98edaf699be9b07d4caa - git-ptx-patches magic
--
2.47.3
^ permalink raw reply [flat|nested] 6+ messages in thread