From: Ahmad Fatoum <a.fatoum@pengutronix.de> To: barebox@lists.infradead.org Cc: Ahmad Fatoum <a.fatoum@pengutronix.de> Subject: [PATCH v2 2/5] RISC-V: cpuinfo: return some output for non-SBI systems as well Date: Mon, 31 May 2021 09:03:22 +0200 [thread overview] Message-ID: <20210531070325.19627-2-a.fatoum@pengutronix.de> (raw) In-Reply-To: <20210531070325.19627-1-a.fatoum@pengutronix.de> If barebox managed to actually execute the cpuinfo command, it probably means that it's assumption which instructon set is being used and whether it runs in machine or supervisor mode is correct. Add that output to cpuinfo, so it shows at least something for non-SBI configurations. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> --- v1 -> v2: - new patch after feedback from Antony --- arch/riscv/include/asm/sbi.h | 8 ++---- arch/riscv/lib/cpuinfo.c | 55 +++++++++++++++++++++++++----------- commands/Kconfig | 4 +-- 3 files changed, 43 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ab1fc9a128e5..eb4018de382e 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -9,9 +9,7 @@ #include <linux/types.h> -#ifdef CONFIG_RISCV_SBI enum sbi_ext_id { -#ifdef CONFIG_RISCV_SBI_V01 SBI_EXT_0_1_SET_TIMER = 0x0, SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, @@ -21,7 +19,7 @@ enum sbi_ext_id { SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, SBI_EXT_0_1_SHUTDOWN = 0x8, -#endif + SBI_EXT_BASE = 0x10, SBI_EXT_TIME = 0x54494D45, SBI_EXT_IPI = 0x735049, @@ -167,7 +165,5 @@ static inline unsigned long sbi_minor_version(void) } int sbi_err_map_linux_errno(int err); -#else /* CONFIG_RISCV_SBI */ -static inline int sbi_remote_fence_i(const unsigned long *hart_mask) { return -1; } -#endif /* CONFIG_RISCV_SBI */ + #endif /* _ASM_RISCV_SBI_H */ diff --git a/arch/riscv/lib/cpuinfo.c b/arch/riscv/lib/cpuinfo.c index 21b99a990a1a..16305e6c4d96 100644 --- a/arch/riscv/lib/cpuinfo.c +++ b/arch/riscv/lib/cpuinfo.c @@ -2,6 +2,7 @@ #include <common.h> #include <command.h> #include <asm/sbi.h> +#include <asm/system.h> static const char *implementations[] = { [0] = "\"Berkeley Boot Loader (BBL)\" ", @@ -12,34 +13,56 @@ static const char *implementations[] = { [5] = "\"Diosix\" ", }; +static const char *modes[] = { + [RISCV_U_MODE] = "U", + [RISCV_S_MODE] = "S", + [RISCV_HS_MODE] = "HS", + [RISCV_M_MODE] = "M", +}; + static int do_cpuinfo(int argc, char *argv[]) { const char *implementation = ""; + enum riscv_mode mode; unsigned long impid; - printf("SBI specification v%lu.%lu detected\n", - sbi_major_version(), sbi_minor_version()); + mode = riscv_mode() & RISCV_MODE_MASK; + + printf("%s barebox for %s-Mode\n", + IS_ENABLED(CONFIG_ARCH_RV64I) ? "RV64I" : "RV32I", + modes[mode]); + + switch (mode) { + case RISCV_S_MODE: + if (!IS_ENABLED(CONFIG_RISCV_SBI)) + break; + printf("SBI specification v%lu.%lu detected\n", + sbi_major_version(), sbi_minor_version()); - if (sbi_spec_is_0_1()) - return 0; + if (sbi_spec_is_0_1()) + return 0; - impid = __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_ID); - if (impid < ARRAY_SIZE(implementations)) - implementation = implementations[impid]; + impid = __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_ID); + if (impid < ARRAY_SIZE(implementations)) + implementation = implementations[impid]; - printf("SBI implementation ID=0x%lx %sVersion=0x%lx\n", - impid, implementation, __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION)); + printf("SBI implementation ID=0x%lx %sVersion=0x%lx\n", + impid, implementation, __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION)); - printf("SBI Machine VENDORID=0x%lx ARCHID=0x%lx MIMPID=0x%lx\n", - __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID), - __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID), - __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID)); + printf("SBI Machine VENDORID=0x%lx ARCHID=0x%lx MIMPID=0x%lx\n", + __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID), + __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID), + __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID)); + break; + default: + break; + } return 0; } BAREBOX_CMD_START(cpuinfo) .cmd = do_cpuinfo, -BAREBOX_CMD_DESC("show CPU information") -BAREBOX_CMD_GROUP(CMD_GRP_INFO) - BAREBOX_CMD_END + BAREBOX_CMD_DESC("show CPU information") + BAREBOX_CMD_GROUP(CMD_GRP_INFO) +BAREBOX_CMD_END diff --git a/commands/Kconfig b/commands/Kconfig index 5ae3cb3dd145..6da68a7f1467 100644 --- a/commands/Kconfig +++ b/commands/Kconfig @@ -47,9 +47,9 @@ config CMD_ARM_CPUINFO config CMD_RISCV_CPUINFO bool "cpuinfo command" default y - depends on RISCV_SBI + depends on RISCV help - Show SBI info about RISC-V CPU + Show info about RISC-V CPU config CMD_DEVINFO tristate -- 2.29.2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
next prev parent reply other threads:[~2021-05-31 7:04 UTC|newest] Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-31 7:03 [PATCH v2 1/5] RISC-V: extend multi-image to support both S- and M-Mode Ahmad Fatoum 2021-05-31 7:03 ` Ahmad Fatoum [this message] 2021-05-31 7:03 ` [PATCH v2 3/5] clocksource: RISC-V: demote probe success messages to debug level Ahmad Fatoum 2021-05-31 7:03 ` [PATCH v2 4/5] RISC-V: S-Mode: propagate Hart ID Ahmad Fatoum 2021-05-31 7:05 ` Ahmad Fatoum 2021-05-31 7:03 ` [PATCH v2 5/5] RISC-V: erizo: make it easier to reuse ns16550 debug_ll Ahmad Fatoum 2021-06-07 7:42 ` [PATCH v2 1/5] RISC-V: extend multi-image to support both S- and M-Mode Ahmad Fatoum
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