From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH 4/9] RISC-V: virt: riscvemu: repurpose 64k low RAM for state/environment
Date: Sat, 8 Jan 2022 18:15:19 +0100 [thread overview]
Message-ID: <20220108171524.587144-4-a.fatoum@pengutronix.de> (raw)
In-Reply-To: <20220108171524.587144-1-a.fatoum@pengutronix.de>
TinyEMU's RISC-V machine emulates a 64K SRAM at address 0.
First 4K page is unused, then a maximum of 0x40 bytes for boot ROM
(trampoline that passes FDT), then the FDT. The remainder of the 64K is
unused. Make use of that space for storing state and environment.
We start the mtd-ram at 0x1000 to easily allow for a faulting zero page.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/boards/riscvemu/Makefile | 1 +
arch/riscv/boards/riscvemu/board.c | 9 ++
.../riscv/boards/riscvemu/overlay-of-sram.dts | 119 ++++++++++++++++++
arch/riscv/configs/virt32_defconfig | 1 +
arch/riscv/configs/virt64_defconfig | 1 +
5 files changed, 131 insertions(+)
create mode 100644 arch/riscv/boards/riscvemu/overlay-of-sram.dts
diff --git a/arch/riscv/boards/riscvemu/Makefile b/arch/riscv/boards/riscvemu/Makefile
index ad283446eaf1..75f52ada8f37 100644
--- a/arch/riscv/boards/riscvemu/Makefile
+++ b/arch/riscv/boards/riscvemu/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += board.o
+obj-y += overlay-of-sram.dtb.o
diff --git a/arch/riscv/boards/riscvemu/board.c b/arch/riscv/boards/riscvemu/board.c
index 73d787a8335a..60c93716a2bc 100644
--- a/arch/riscv/boards/riscvemu/board.c
+++ b/arch/riscv/boards/riscvemu/board.c
@@ -7,6 +7,7 @@
#include <driver.h>
#include <poweroff.h>
#include <restart.h>
+#include <deep-probe.h>
#include <asm/system.h>
#include <asm/barebox-riscv.h>
@@ -28,12 +29,19 @@ static void __noreturn riscvemu_restart(struct restart_handler *rst)
priv->restart(riscv_hartid(), barebox_riscv_boot_dtb());
}
+extern char __dtb_overlay_of_sram_start[];
+
static int riscvemu_probe(struct device_d *dev)
{
struct device_node *of_chosen;
+ struct device_node *overlay;
struct riscvemu_priv *priv;
u64 start;
+ overlay = of_unflatten_dtb(__dtb_overlay_of_sram_start, INT_MAX);
+ of_overlay_apply_tree(dev->device_node, overlay);
+ /* of_probe() will happen later at of_populate_initcall */
+
of_chosen = of_find_node_by_path("/chosen");
if (of_property_read_u64(of_chosen, "riscv,kernel-start", &start))
@@ -52,6 +60,7 @@ static const struct of_device_id riscvemu_of_match[] = {
{ .compatible = "ucbbar,riscvemu-bar_dev" },
{ /* sentinel */ },
};
+BAREBOX_DEEP_PROBE_ENABLE(riscvemu_of_match);
static struct driver_d riscvemu_board_driver = {
.name = "board-riscvemu",
diff --git a/arch/riscv/boards/riscvemu/overlay-of-sram.dts b/arch/riscv/boards/riscvemu/overlay-of-sram.dts
new file mode 100644
index 000000000000..839887fef24c
--- /dev/null
+++ b/arch/riscv/boards/riscvemu/overlay-of-sram.dts
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target-path = "/soc";
+ __overlay__ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ sram@0 {
+ compatible = "mtd-ram";
+ reg = <0 0x1000 0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bootrom";
+ reg = <0x0 0x40>;
+ };
+
+ partition@40 {
+ label = "fdt";
+ reg = <0x40 0x1fc0>;
+ };
+
+ environment_sram: partition@3000 {
+ label = "barebox-environment";
+ reg = <0x3000 0xb000>;
+ };
+
+ backend_state_sram: partition@e000 {
+ label = "barebox-state";
+ reg = <0xe000 0x1000>;
+ };
+ };
+ };
+ };
+ };
+
+ fragment@2 {
+ target-path = "/chosen";
+ __overlay__ {
+ environment {
+ compatible = "barebox,environment";
+ device-path = "/soc/sram@0/partitions/partition@3000";
+ };
+ };
+ };
+
+ fragment@3 {
+ target-path = "/";
+ __overlay__ {
+ aliases {
+ state = "/state";
+ };
+
+ state {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "barebox,state";
+ magic = <0x290cf8c6>;
+ backend-type = "raw";
+ backend = <&backend_state_sram>;
+ backend-stridesize = <64>;
+
+ bootstate {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ system0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ remaining_attempts@0 {
+ reg = <0x0 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+
+ priority@4 {
+ reg = <0x4 0x4>;
+ type = "uint32";
+ default = <20>;
+ };
+ };
+
+ system1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ remaining_attempts@8 {
+ reg = <0x8 0x4>;
+ type = "uint32";
+ default = <3>;
+ };
+
+ priority@c {
+ reg = <0xc 0x4>;
+ type = "uint32";
+ default = <21>;
+ };
+ };
+
+ last_chosen@10 {
+ reg = <0x10 0x4>;
+ type = "uint32";
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/riscv/configs/virt32_defconfig b/arch/riscv/configs/virt32_defconfig
index bfea7771efd8..28a20673e9b7 100644
--- a/arch/riscv/configs/virt32_defconfig
+++ b/arch/riscv/configs/virt32_defconfig
@@ -88,6 +88,7 @@ CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_MTD_CONCAT=y
CONFIG_MTD_M25P80=y
+CONFIG_MTD_MTDRAM=y
CONFIG_DRIVER_CFI=y
CONFIG_DRIVER_CFI_BANK_WIDTH_8=y
CONFIG_DISK=y
diff --git a/arch/riscv/configs/virt64_defconfig b/arch/riscv/configs/virt64_defconfig
index 2ddc174b8a65..17588f61fa35 100644
--- a/arch/riscv/configs/virt64_defconfig
+++ b/arch/riscv/configs/virt64_defconfig
@@ -89,6 +89,7 @@ CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_MTD_CONCAT=y
CONFIG_MTD_M25P80=y
+CONFIG_MTD_MTDRAM=y
CONFIG_DRIVER_CFI=y
CONFIG_DRIVER_CFI_BANK_WIDTH_8=y
CONFIG_DISK=y
--
2.30.2
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next prev parent reply other threads:[~2022-01-08 17:17 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-08 17:15 [PATCH 1/9] RISC-V: virt: activate all consoles Ahmad Fatoum
2022-01-08 17:15 ` [PATCH 2/9] power: reset: add RISC-V/UC Berkely HTIF poweroff driver support Ahmad Fatoum
2022-01-08 17:15 ` [PATCH 3/9] RISC-V: virt: riscvemu: add HTIF DEBUG_LL support Ahmad Fatoum
2022-01-08 17:15 ` Ahmad Fatoum [this message]
2022-01-08 17:15 ` [PATCH 5/9] RISC-V: virt: riscvemu: be explicit about HTIF base address Ahmad Fatoum
2022-01-08 17:15 ` [PATCH 6/9] RISC-V: virt: riscvemu: clear frame buffer before jumping to reset vector Ahmad Fatoum
2022-01-08 17:15 ` [PATCH 7/9] RISC-V: don't use x8/s0/fp in assembly Ahmad Fatoum
2022-01-08 18:25 ` Ahmad Fatoum
2022-01-10 10:59 ` Antony Pavlov
2022-01-08 17:15 ` [PATCH 8/9] RISC-V: add stacktrace support via frame pointer walking Ahmad Fatoum
2022-01-08 17:15 ` [PATCH 9/9] RISC-V: Virt: enable more useful options Ahmad Fatoum
2022-01-12 10:23 ` [PATCH 1/9] RISC-V: virt: activate all consoles Sascha Hauer
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