From: Jules Maselbas <jmaselbas@kalray.eu>
To: barebox@lists.infradead.org
Cc: Clement Leger <clement.leger@bootlin.com>,
Louis Morhet <lmorhet@kalray.eu>, Luc Michel <lmichel@kalray.eu>,
Yann Sionneau <ysionneau@kalray.eu>,
Jules Maselbas <jmaselbas@kalray.eu>
Subject: [PATCH 13/13] kvx: dts: Update k200.dts
Date: Fri, 14 Jan 2022 17:54:56 +0100 [thread overview]
Message-ID: <20220114165456.10542-4-jmaselbas@kalray.eu> (raw)
In-Reply-To: <20220114165456.10542-1-jmaselbas@kalray.eu>
Signed-off-by: Jules Maselbas <jmaselbas@kalray.eu>
---
arch/kvx/dts/k200.dts | 426 ++++++++++++++++++++++++++++++++++++++++--
1 file changed, 410 insertions(+), 16 deletions(-)
diff --git a/arch/kvx/dts/k200.dts b/arch/kvx/dts/k200.dts
index d463ffda50..e83a08b462 100644
--- a/arch/kvx/dts/k200.dts
+++ b/arch/kvx/dts/k200.dts
@@ -3,6 +3,8 @@
* Copyright (C) 2019 Kalray, Inc.
*/
+#include <dt-bindings/interrupt-controller/irq.h>
+
/dts-v1/;
/ {
@@ -15,7 +17,7 @@
/* Standard nodes (choosen, cpus, memory, etc) */
chosen {
bootargs = "earlycon norandmaps console=ttyS0";
- stdout-path = &serial0;
+ stdout-path = &uart0;
};
cpus {
@@ -46,6 +48,13 @@
/* 1 GHz clock */
clock-frequency = <1000000000>;
};
+
+ socp_clk: socp_clk@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ /* 480 MHz clock */
+ clock-frequency = <480000000>;
+ };
};
ddr: memory@100000000 {
@@ -60,44 +69,147 @@
reg = <0x0 0x0 0x0 0x400000>;
};
+ core_intc: core_intc@0 {
+ compatible = "kalray,kvx-core-intc";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ ipi_ctrl: ipi_ctrl@ad0000 {
+ compatible = "kalray,kvx-ipi-ctrl";
+ reg = <0x0 0xad0000 0x0 0x1000>;
+ interrupt-parent = <&core_intc>;
+ interrupts = <24>;
+ };
+
+ apic_gic: apic_gic@a20000 {
+ compatible = "kalray,kvx-apic-gic";
+ reg = <0x0 0xa20000 0x0 0x12000>;
+ #address-cells = <0>;
+ interrupt-parent = <&core_intc>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <4 5 6 7>;
+ };
+
+ apic_mailbox: apic_mailbox@a00000 {
+ compatible = "kalray,kvx-apic-mailbox";
+ reg = <0x0 0xa00000 0x0 0xea00>;
+ #address-cells = <0>;
+ interrupt-parent = <&apic_gic>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ interrupts = <0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100 101 102 103 104 105 106 107 108 109
+ 110 111 112 113 114 115 116>;
+ msi-controller;
+ };
+
+ dame_handler {
+ /* Data Asynchronous Memory Error handler */
+ compatible = "kalray,kvx-dame-handler";
+ interrupt-parent = <&core_intc>;
+ interrupts = <16>;
+ };
+
core_timer {
compatible = "kalray,kvx-core-timer";
+ interrupts = <0>;
+ interrupt-parent = <&core_intc>;
clocks = <&core_clk>;
};
core_watchdog {
compatible = "kalray,kvx-core-watchdog";
+ interrupts = <2>;
+ interrupt-parent = <&core_intc>;
+ clocks = <&core_clk>;
+ };
+
+ core_pm {
+ compatible = "kalray,kvx-core-pm";
+ interrupts = <3>;
+ interrupt-parent = <&core_intc>;
+ kalray,pm-num = <4>;
+ };
+
+ pwr_ctrl0: pwr_ctrl@a40000 {
+ reg = <0x0 0xa40000 0x0 0x4158>;
+ compatible = "kalray,kvx-pwr-ctrl";
+ };
+
+ power_off {
+ compatible = "kalray,kvx-scall-poweroff";
+ };
+
+ dsu_clock {
+ compatible = "kalray,kvx-dsu-clock";
+ reg = <0x0 0xa44180 0x0 0x8>;
clocks = <&core_clk>;
};
- axi {
+ axi: axi {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges;
+
+ iommu_soc_periph: iommu_soc_periph@27020000 {
+ compatible = "kalray,kvx-iommu";
+ reg = <0x0 0x27020000 0x0 0x00000240>,
+ <0x0 0x27020800 0x0 0x00000240>;
+ reg-names = "tx", "rx";
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, <0 IRQ_TYPE_LEVEL_HIGH>, <5 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>, <15 IRQ_TYPE_LEVEL_HIGH>, <20 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rx_nomapping", "rx_protection", "rx_parity",
+ "tx_nomapping", "tx_protection", "tx_parity";
+ interrupt-parent = <&itgen_soc_periph1>;
+ #iommu-cells = <1>;
+ };
+
+ itgen_soc_periph0: itgen_soc_periph0@27000000 {
+ compatible = "kalray,kvx-itgen";
+ reg = <0x0 0x27000000 0x0 0x1104>;
+ #address-cells = <0>;
+ msi-parent = <&apic_mailbox>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ itgen_soc_periph1: itgen_soc_periph1@27010000 {
+ compatible = "kalray,kvx-itgen";
+ reg = <0x0 0x27010000 0x0 0x1104>;
+ #address-cells = <0>;
+ msi-parent = <&apic_mailbox>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
ftu: ftu@10181000 {
compatible = "kalray,kvx-syscon", "syscon";
reg = <0x0 0x10181000 0x0 0x410>;
};
- pmx_gpio0: pinmux@20230008 {
- compatible = "pinctrl-single";
- reg = <0x0 0x20230008 0x0 0x4>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <2>;
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x1>;
-
- uart0_pins: pinmux_uart0_pins {
- pinctrl-single,bits = <0x00 0x00000003 0x00000003>;
- };
+ reboot: reboot@0 {
+ compatible = "syscon-reboot";
+ regmap = <&ftu>;
+ offset = <0x50>;
+ value = <0x1>;
};
- serial0: uart0@20210000 {
+ uart0: uart0@20210000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x20210000 0x0 0x100>;
clocks = <&ref_clk>;
@@ -105,6 +217,288 @@
reg-shift = <2>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
+ interrupt-parent = <&itgen_soc_periph0>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart1: uart1@20211000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20211000 0x0 0x100>;
+ clocks = <&ref_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ interrupt-parent = <&itgen_soc_periph0>;
+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart2: uart2@20212000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20212000 0x0 0x100>;
+ clocks = <&ref_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ interrupt-parent = <&itgen_soc_periph0>;
+ interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart3: uart3@20213000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20213000 0x0 0x100>;
+ clocks = <&ref_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ interrupt-parent = <&itgen_soc_periph0>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart4: uart4@20214000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20214000 0x0 0x100>;
+ clocks = <&ref_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+ interrupt-parent = <&itgen_soc_periph0>;
+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart5: uart5@20215000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20215000 0x0 0x100>;
+ clocks = <&ref_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_pins>;
+ interrupt-parent = <&itgen_soc_periph0>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timers0: timers0@20220000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x0 0x20220000 0x0 0xD0>;
+ clocks = <&ref_clk>;
+ };
+
+ timers4: timers4@20224000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0x0 0x20224000 0x0 0xD0>;
+ clocks = <&ref_clk>;
+ };
+
+ otp_nv: otp_nv_regs@d20000 {
+ reg = <0x0 0xd20000 0x0 0xe0>;
+ compatible = "kalray,kvx-otp-nv";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ft_fuse: ft_fuse@cc {
+ reg = <0xcc 0x4>;
+ };
+ ews_fuse: ews_fuse@d8 {
+ reg = <0xd8 0x8>;
+ };
+ };
+
+ kvx_socinfo: kvx_socinfo@0 {
+ compatible = "kalray,kvx-socinfo";
+ nvmem-cells = <&ews_fuse>, <&ft_fuse>;
+ nvmem-cell-names = "ews_fuse", "ft_fuse";
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>;
+
+ usb0: usb0@20080000 {
+ compatible = "kalray,kvx-hsotg", "snps,dwc2";
+ reg = <0x0 0x20080000 0x0 0x40000>;
+ clocks = <&socp_clk>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ interrupt-parent = <&itgen_soc_periph0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ g-rx-fifo-size = <2048>;
+ g-np-tx-fifo-size = <512>;
+ g-tx-fifo-size = <512 512 512 512 512 512 512 512>;
+ iommus = <&iommu_soc_periph 0x18>;
+ };
+
+ usb1: usb1@20100000 {
+ compatible = "kalray,kvx-hsotg", "snps,dwc2";
+ reg = <0x0 0x20100000 0x0 0x40000>;
+ clocks = <&socp_clk>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ interrupt-parent = <&itgen_soc_periph0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ g-rx-fifo-size = <2048>;
+ g-np-tx-fifo-size = <512>;
+ g-tx-fifo-size = <512 512 512 512 512 512 512 512>;
+ iommus = <&iommu_soc_periph 0x28>;
+ };
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@20230000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x0 0x20230000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio0_banka: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ #address-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ snps,has-pinctrl;
+ reg = <0>;
+ interrupt-parent = <&itgen_soc_periph0>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+ /* All pins of port A are interrupt capable */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart0_pins: pinmux_uart0_pins {
+ function = "hw";
+ pins = "pin0", "pin1";
+ };
+ uart1_pins: pinmux_uart1_pins {
+ function = "hw";
+ pins = "pin2", "pin3";
+ };
+ uart2_pins: pinmux_uart2_pins {
+ function = "hw";
+ pins = "pin4", "pin5";
+ };
+ can0_pins: pinmux_can0_pins {
+ function = "hw";
+ pins = "pin6", "pin7";
+ };
+ can1_pins: pinmux_can1_pins {
+ function = "hw";
+ pins = "pin8", "pin9";
+ };
+ i2c0_pins: pinmux_i2c0_pins {
+ function = "hw";
+ pins = "pin10", "pin11";
+ };
+ smb1_pins: pinmux_smb1_pins {
+ function = "hw";
+ pins = "pin12", "pin13";
+ };
+ smb2_pins: pinmux_smb2_pins {
+ function = "hw";
+ pins = "pin14", "pin15";
+ };
+ qspi0_master_pins:pinmux_qspi0_master_pins {
+ function = "hw";
+ pins = "pin18", "pin19", "pin20", "pin21", "pin22", "pin23", "pin24";
+ };
+ spi_slave_pins:pinmux_spi_slave_pins {
+ function = "hw";
+ pins = "pin25", "pin26", "pin27", "pin28";
+ };
+ timer0_pins:pinmux_timer0_pins {
+ function = "hw";
+ pins = "pin29";
+ };
+ timer1_pins:pinmux_timer1_pins {
+ function = "hw";
+ pins = "pin30";
+ };
+ timer2_pins:pinmux_timer2_pins {
+ function = "hw";
+ pins = "pin31";
+ };
+ };
+ };
+
+ gpio1: gpio@20231000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x0 0x20231000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1_banka: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ #address-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ snps,has-pinctrl;
+ reg = <0>;
+ interrupt-parent = <&itgen_soc_periph0>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+ /* All pins of port A are interrupt capable */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart3_pins: pinmux_uart3_pins {
+ function = "hw";
+ pins = "pin0", "pin1";
+ };
+ uart4_pins: pinmux_uart4_pins {
+ function = "hw";
+ pins = "pin2", "pin3";
+ };
+ uart5_pins: pinmux_uart5_pins {
+ function = "hw";
+ pins = "pin4", "pin5";
+ };
+ can2_pins: pinmux_can2_pins {
+ function = "hw";
+ pins = "pin6", "pin7";
+ };
+ can3_pins: pinmux_can3_pins {
+ function = "hw";
+ pins = "pin8", "pin9";
+ };
+ i2c3_pins: pinmux_i2c3_pins {
+ function = "hw";
+ pins = "pin10", "pin11";
+ };
+ smb4_pins: pinmux_smb4_pins {
+ function = "hw";
+ pins = "pin12", "pin13";
+ };
+ timer3_pins:pinmux_timer3_pins {
+ function = "hw";
+ pins = "pin15";
+ };
+ timer4_pins:pinmux_timer4_pins {
+ function = "hw";
+ pins = "pin16";
+ };
+ timer5_pins:pinmux_timer5_pins {
+ function = "hw";
+ pins = "pin17";
+ };
+ qspi1_master_pins:pinmux_qspi1_master_pins {
+ function = "hw";
+ pins = "pin18", "pin19", "pin20", "pin21", "pin22", "pin23", "pin24";
+ };
+ qspi2_master_pins:pinmux_qspi2_master_pins {
+ function = "hw";
+ pins = "pin25", "pin26", "pin27", "pin28", "pin29", "pin30", "pin31";
+ };
+ };
+ };
};
};
};
--
2.17.1
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next prev parent reply other threads:[~2022-01-14 16:56 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-14 16:51 [PATCH 00/13] kvx arch update Jules Maselbas
2022-01-14 16:52 ` [PATCH 01/13] kvx: dma: Remove arch dma_map/unmap_single Jules Maselbas
2022-01-14 16:52 ` [PATCH 02/13] kvx: Move LINUX_BOOT_PARAM_MAGIC in asm/common.h Jules Maselbas
2022-01-14 16:52 ` [PATCH 03/13] kvx: Accept LINUX_BOOT_PARAM_MAGIC as a valid magic value Jules Maselbas
2022-01-14 16:52 ` [PATCH 04/13] common: elf: add elf_load_binary Jules Maselbas
2022-01-14 17:21 ` Clément Léger
2022-01-14 17:24 ` Jules Maselbas
2022-01-14 16:52 ` [PATCH 05/13] kvx: enable FITIMAGE support Jules Maselbas
2022-01-14 16:52 ` [PATCH 06/13] clocksource: kvx: Register as postcore_platform_driver Jules Maselbas
2022-01-14 16:52 ` [PATCH 07/13] watchdog: kvx: do not disable watchdog on probe Jules Maselbas
2022-01-14 16:52 ` [PATCH 08/13] nvmem: add kvx otp non volatile regbank support Jules Maselbas
2022-01-17 8:24 ` Sascha Hauer
2022-01-17 11:17 ` Jules Maselbas
2022-01-14 16:52 ` [PATCH 09/13] kvx: add kvx_sfr_field_val Jules Maselbas
2022-01-14 16:54 ` [PATCH 10/13] drivers: add soc hierarchy properly Jules Maselbas
2022-01-14 16:54 ` [PATCH 11/13] soc: add kvx_socinfo driver Jules Maselbas
2022-01-14 16:54 ` [PATCH 12/13] kvx: Update defconfig Jules Maselbas
2022-01-14 16:54 ` Jules Maselbas [this message]
2022-01-14 17:31 ` [PATCH 13/13] kvx: dts: Update k200.dts Clément Léger
2022-01-14 17:06 ` [PATCH 10/13] drivers: add soc hierarchy properly Ahmad Fatoum
2022-01-14 17:11 ` Jules Maselbas
2022-01-14 17:20 ` Ahmad Fatoum
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