[PATCH v2 0/4] clk: socfpga: agilex5: sync with kernel

[PATCH v2 0/4] clk: socfpga: agilex5: sync with kernel

[Michael Tretter]

This is a v2 of the patch series [0] to synchronize the socfpga clock
driver with the kernel driver, which was applied by reverted due to a
compile error.

This series split the original patch into cleanup patches to synchronize
the entire socfpga clock driver with the Linux driver and another patch
to apply the synchronization of the actual Agilex5 driver. Otherwise,
the fix of the compile error would have resulted in inconsistent structs
for the various clocks.

I runtime tested this patch series only on Agilex 5, and only did build
tests on the other SoCFPGA platforms.

[0] https://lore.kernel.org/all/20251215-v2025-11-0-topic-socfpga-agilex5-clk-v1-1-e1270179d761@pengutronix.de/

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
Michael Tretter (2):
      clk: socfpga: sync arria10 clock initialization with kernel
      clk: socfpga: remove clk-phase setting

Steffen Trumtrar (2):
      clk: socfpga: sync clock structs with kernel
      clk: socfpga: agilex5: sync with kernel

 drivers/clk/socfpga/clk-agilex5.c    | 842 ++++++++++++-----------------------
 drivers/clk/socfpga/clk-gate-a10.c   | 104 +----
 drivers/clk/socfpga/clk-gate-s10.c   |  32 +-
 drivers/clk/socfpga/clk-periph-a10.c |  39 +-
 drivers/clk/socfpga/clk-periph-s10.c |  66 ++-
 drivers/clk/socfpga/clk-pll-a10.c    |  56 +--
 drivers/clk/socfpga/clk-pll-s10.c    |  57 ++-
 drivers/clk/socfpga/clk.h            |  15 +-
 drivers/clk/socfpga/stratix10-clk.h  |  48 +-
 9 files changed, 498 insertions(+), 761 deletions(-)
---
base-commit: 713a1e59dfea4516446822323b7c0db571cb214f
change-id: 20260604-socfpga-agilex5-clk-50bede6b1c8d

Best regards,
-- 
Michael Tretter <m.tretter@pengutronix.de>

[PATCH v2 1/4] clk: socfpga: sync arria10 clock initialization with kernel

[Michael Tretter]

Switch from bclk_register to clk_hw_register with clk_init_data to be
more in line with the Linux driver.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/clk/socfpga/clk-gate-a10.c   | 27 ++++++++++++---------------
 drivers/clk/socfpga/clk-periph-a10.c | 29 ++++++++++++++---------------
 drivers/clk/socfpga/clk-pll-a10.c    | 31 ++++++++++++++++---------------
 3 files changed, 42 insertions(+), 45 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index b66fbcdb8c54..e6bcc91b0490 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -117,10 +117,12 @@ static struct clk *__socfpga_gate_init(struct device_node *node,
 	u32 div_reg[3];
 	u32 clk_phase[2];
 	u32 fixed_div;
+	struct clk_hw *hw_clk;
 	struct socfpga_gate_clk *socfpga_clk;
 	const char *clk_name = node->name;
+	const char *parent_name[SOCFPGA_MAX_PARENTS];
+	struct clk_init_data init;
 	int rc;
-	int i;
 
 	socfpga_clk = xzalloc(sizeof(*socfpga_clk));
 
@@ -159,23 +161,18 @@ static struct clk *__socfpga_gate_init(struct device_node *node,
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
-	socfpga_clk->hw.clk.name = xstrdup(clk_name);
-	socfpga_clk->hw.clk.ops = ops;
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
 
-	for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) {
-		socfpga_clk->parent_names[i] = of_clk_get_parent_name(node, i);
-		if (!socfpga_clk->parent_names[i])
-			break;
-	}
+	init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
+	init.parent_names = parent_name;
+	socfpga_clk->hw.init = &init;
+	hw_clk = &socfpga_clk->hw;
 
-	socfpga_clk->hw.clk.num_parents = i;
-	socfpga_clk->hw.clk.parent_names = socfpga_clk->parent_names;
-
-	rc = bclk_register(&socfpga_clk->hw.clk);
-	if (rc) {
-		free(socfpga_clk);
+	rc = clk_hw_register(NULL, hw_clk);
+	if (rc)
 		return ERR_PTR(rc);
-	}
 
 	return &socfpga_clk->hw.clk;
 }
diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
index f9cf40b0aaf3..61b693d295f7 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -62,12 +62,14 @@ static struct clk *__socfpga_periph_init(struct device_node *node,
 	const struct clk_ops *ops)
 {
 	u32 reg;
+	struct clk_hw *hw_clk;
 	struct socfpga_periph_clk *periph_clk;
 	const char *clk_name = node->name;
+	const char *parent_name[SOCFPGA_MAX_PARENTS];
+	struct clk_init_data init;
 	int rc;
 	u32 fixed_div;
 	u32 div_reg[3];
-	int i;
 
 	of_property_read_u32(node, "reg", &reg);
 
@@ -92,25 +94,22 @@ static struct clk *__socfpga_periph_init(struct device_node *node,
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
-	for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) {
-		periph_clk->parent_names[i] = of_clk_get_parent_name(node, i);
-		if (!periph_clk->parent_names[i])
-			break;
-	}
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
 
-	periph_clk->hw.clk.num_parents = i;
-	periph_clk->hw.clk.parent_names = periph_clk->parent_names;
+	init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
+	init.parent_names = parent_name;
 
-	periph_clk->hw.clk.name = xstrdup(clk_name);
-	periph_clk->hw.clk.ops = ops;
+	periph_clk->hw.init = &init;
 
-	rc = bclk_register(&periph_clk->hw.clk);
-	if (rc) {
-		free(periph_clk);
+	hw_clk = &periph_clk->hw;
+
+	rc = clk_hw_register(NULL, hw_clk);
+	if (rc)
 		return ERR_PTR(rc);
-	}
 
-	return &periph_clk->hw.clk;
+	return &hw_clk->clk;
 }
 
 struct clk *socfpga_a10_periph_init(struct device_node *node)
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index 2e58a2eb5d92..566d99563ff6 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -88,10 +88,13 @@ static struct clk *__socfpga_pll_init(struct device_node *node,
 	const struct clk_ops *ops)
 {
 	u32 reg;
+	struct clk_hw *hw_clk;
 	struct socfpga_pll *pll_clk;
 	const char *clk_name = node->name;
+	const char *parent_name[SOCFGPA_MAX_PARENTS];
+	struct clk_init_data init;
 	int rc;
-	int i;
+	int i = 0;
 
 	of_property_read_u32(node, "reg", &reg);
 
@@ -101,27 +104,25 @@ static struct clk *__socfpga_pll_init(struct device_node *node,
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
-	pll_clk->hw.clk.name = xstrdup(clk_name);
-	pll_clk->hw.clk.ops = ops;
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
 
-	for (i = 0; i < SOCFPGA_MAX_PARENTS; i++) {
-		pll_clk->parent_names[i] = of_clk_get_parent_name(node, i);
-		if (!pll_clk->parent_names[i])
-			break;
-	}
+	while (i < SOCFGPA_MAX_PARENTS &&
+	       (parent_name[i] = of_clk_get_parent_name(node, i)) != NULL)
+		i++;
+	init.num_parents = i;
+	init.parent_names = parent_name;
 
 	pll_clk->bit_idx = SOCFPGA_PLL_EXT_ENA;
-	pll_clk->hw.clk.num_parents = i;
-	pll_clk->hw.clk.parent_names = pll_clk->parent_names;
+	hw_clk = &pll_clk->hw;
 
 	clk_pll_ops.enable = clk_socfpga_enable;
 	clk_pll_ops.disable = clk_socfpga_disable;
 
-	rc = bclk_register(&pll_clk->hw.clk);
-	if (rc) {
-		free(pll_clk);
-		return NULL;
-	}
+	rc = clk_hw_register(NULL, &pll_clk->hw);
+	if (rc)
+		ERR_PTR(rc);
 
 	return &pll_clk->hw.clk;
 }

-- 
2.47.3

[PATCH v2 2/4] clk: socfpga: remove clk-phase setting

[Michael Tretter]

There are no device trees that have the clk-phase property and the Linux
driver doesn't have the code. Remove the unused clk-phase setting.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/clk/socfpga/clk-gate-a10.c | 55 --------------------------------------
 1 file changed, 55 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index e6bcc91b0490..b43e19d2ca3f 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -36,59 +36,11 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hw,
 	return parent_rate / div;
 }
 
-static int socfpga_clk_prepare(struct clk_hw *hw)
-{
-	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hw);
-	int i;
-	u32 hs_timing;
-	u32 clk_phase[2];
-
-	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
-		for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
-			switch (socfpgaclk->clk_phase[i]) {
-			case 0:
-				clk_phase[i] = 0;
-				break;
-			case 45:
-				clk_phase[i] = 1;
-				break;
-			case 90:
-				clk_phase[i] = 2;
-				break;
-			case 135:
-				clk_phase[i] = 3;
-				break;
-			case 180:
-				clk_phase[i] = 4;
-				break;
-			case 225:
-				clk_phase[i] = 5;
-				break;
-			case 270:
-				clk_phase[i] = 6;
-				break;
-			case 315:
-				clk_phase[i] = 7;
-				break;
-			default:
-				clk_phase[i] = 0;
-				break;
-			}
-		}
-
-		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
-		writel(hs_timing, ARRIA10_SYSMGR_SDMMC);
-	}
-	return 0;
-}
-
 static int clk_socfpga_enable(struct clk_hw *hw)
 {
 	struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(hw);
 	u32 val;
 
-	socfpga_clk_prepare(hw);
-
 	val = readl(socfpga_clk->reg);
 	val |= 1 << socfpga_clk->bit_idx;
 	writel(val, socfpga_clk->reg);
@@ -115,7 +67,6 @@ static struct clk *__socfpga_gate_init(struct device_node *node,
 {
 	u32 clk_gate[2];
 	u32 div_reg[3];
-	u32 clk_phase[2];
 	u32 fixed_div;
 	struct clk_hw *hw_clk;
 	struct socfpga_gate_clk *socfpga_clk;
@@ -153,12 +104,6 @@ static struct clk *__socfpga_gate_init(struct device_node *node,
 		socfpga_clk->div_reg = NULL;
 	}
 
-	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
-	if (!rc) {
-		socfpga_clk->clk_phase[0] = clk_phase[0];
-		socfpga_clk->clk_phase[1] = clk_phase[1];
-	}
-
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
 	init.name = clk_name;

-- 
2.47.3

[PATCH v2 3/4] clk: socfpga: sync clock structs with kernel

[Michael Tretter]

From: Steffen Trumtrar <s.trumtrar@pengutronix.de>

Sync struct socfpga_pll, struct socfpga_gate_clk, and struct
socfpga_periph_clk and change the base from clk_hw to clk_gate. This
allows easier syncing with the Linux driver.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/clk/socfpga/clk-gate-a10.c   | 26 +++++++++---------
 drivers/clk/socfpga/clk-gate-s10.c   | 25 ++++++++---------
 drivers/clk/socfpga/clk-periph-a10.c | 14 +++++-----
 drivers/clk/socfpga/clk-periph-s10.c | 28 ++++++++++---------
 drivers/clk/socfpga/clk-pll-a10.c    | 29 ++++++++++----------
 drivers/clk/socfpga/clk-pll-s10.c    | 52 ++++++++++++++++++++++--------------
 drivers/clk/socfpga/clk.h            | 15 +++--------
 7 files changed, 96 insertions(+), 93 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index b43e19d2ca3f..dfa227b3f74e 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -14,7 +14,7 @@
 
 #include "clk.h"
 
-#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw)
+#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 
 /* SDMMC Group for System Manager defines */
 #define SYSMGR_SDMMCGRP_CTRL_OFFSET	0x28
@@ -41,9 +41,9 @@ static int clk_socfpga_enable(struct clk_hw *hw)
 	struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(hw);
 	u32 val;
 
-	val = readl(socfpga_clk->reg);
-	val |= 1 << socfpga_clk->bit_idx;
-	writel(val, socfpga_clk->reg);
+	val = readl(socfpga_clk->hw.reg);
+	val |= 1 << socfpga_clk->hw.bit_idx;
+	writel(val, socfpga_clk->hw.reg);
 
 	return 0;
 }
@@ -53,9 +53,9 @@ static void clk_socfpga_disable(struct clk_hw *hw)
 	struct socfpga_gate_clk *socfpga_clk = to_socfpga_gate_clk(hw);
 	u32 val;
 
-	val = readl(socfpga_clk->reg);
-	val &= ~(1 << socfpga_clk->shift);
-	writel(val, socfpga_clk->reg);
+	val = readl(socfpga_clk->hw.reg);
+	val &= ~(1 << socfpga_clk->hw.shift);
+	writel(val, socfpga_clk->hw.reg);
 }
 
 static struct clk_ops gateclk_ops = {
@@ -63,7 +63,7 @@ static struct clk_ops gateclk_ops = {
 };
 
 static struct clk *__socfpga_gate_init(struct device_node *node,
-	const struct clk_ops *ops)
+				       const struct clk_ops *ops)
 {
 	u32 clk_gate[2];
 	u32 div_reg[3];
@@ -82,8 +82,8 @@ static struct clk *__socfpga_gate_init(struct device_node *node,
 		clk_gate[0] = 0;
 
 	if (clk_gate[0]) {
-		socfpga_clk->reg = clk_mgr_base_addr + clk_gate[0];
-		socfpga_clk->bit_idx = clk_gate[1];
+		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
+		socfpga_clk->hw.bit_idx = clk_gate[1];
 
 		gateclk_ops.enable = clk_socfpga_enable;
 		gateclk_ops.disable = clk_socfpga_disable;
@@ -112,14 +112,14 @@ static struct clk *__socfpga_gate_init(struct device_node *node,
 
 	init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
 	init.parent_names = parent_name;
-	socfpga_clk->hw.init = &init;
-	hw_clk = &socfpga_clk->hw;
+	socfpga_clk->hw.hw.init = &init;
+	hw_clk = &socfpga_clk->hw.hw;
 
 	rc = clk_hw_register(NULL, hw_clk);
 	if (rc)
 		return ERR_PTR(rc);
 
-	return &socfpga_clk->hw.clk;
+	return &hw_clk->clk;
 }
 
 struct clk *socfpga_a10_gate_init(struct device_node *node)
diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c
index c4f51b86740a..8fc8a4ea7b8f 100644
--- a/drivers/clk/socfpga/clk-gate-s10.c
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -1,4 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
+// SPDX-Comment: Origin-URL: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/socfpga/clk-gate-s10.c?id=2050b57ecda040010ec797fb07713889372c5041
 /*
  * Copyright (C) 2017, Intel Corporation
  */
@@ -13,7 +14,7 @@
 #include "clk.h"
 
 #define SOCFPGA_CS_PDBG_CLK	"cs_pdbg_clk"
-#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw)
+#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 
 #define SOCFPGA_EMAC0_CLK		"emac0_clk"
 #define SOCFPGA_EMAC1_CLK		"emac1_clk"
@@ -113,7 +114,7 @@ static int socfpga_agilex_gate_get_parent(struct clk_hw *hwclk)
 	return parent;
 }
 
-static struct clk_ops agilex_gateclk_ops = {
+static const struct clk_ops agilex_gateclk_ops = {
 	.recalc_rate = socfpga_gate_clk_recalc_rate,
 	.get_parent = socfpga_agilex_gate_get_parent,
 };
@@ -132,11 +133,9 @@ struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, voi
 	int ret;
 
 	socfpga_clk = xzalloc(sizeof(*socfpga_clk));
-	socfpga_clk->reg = regbase + clks->gate_reg;
-	socfpga_clk->bit_idx = clks->gate_idx;
 
-	agilex_gateclk_ops.enable = clk_gate_ops.enable;
-	agilex_gateclk_ops.disable = clk_gate_ops.disable;
+	socfpga_clk->hw.reg = regbase + clks->gate_reg;
+	socfpga_clk->hw.bit_idx = clks->gate_idx;
 
 	socfpga_clk->fixed_div = clks->fixed_div;
 
@@ -158,21 +157,19 @@ struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, voi
 		init.ops = &dbgclk_ops;
 	else
 		init.ops = &agilex_gateclk_ops;
+
 	init.name = clks->name;
 	init.flags = clks->flags;
-
 	init.num_parents = clks->num_parents;
 	init.parent_names = parent_name ? &parent_name : NULL;
 	if (init.parent_names == NULL)
 		init.parent_data = clks->parent_data;
-	socfpga_clk->hw.init = &init;
+	socfpga_clk->hw.hw.init = &init;
+	hw_clk = &socfpga_clk->hw.hw;
 
-	hw_clk = &socfpga_clk->hw;
-
-	ret = clk_hw_register(NULL, &socfpga_clk->hw);
-	if (ret) {
-		kfree(socfpga_clk);
+	ret = clk_hw_register(NULL, &socfpga_clk->hw.hw);
+	if (ret)
 		return ERR_PTR(ret);
-	}
+
 	return hw_clk;
 }
diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
index 61b693d295f7..b120139bf32b 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -17,7 +17,7 @@
 #define SOCFPGA_MPU_FREE_CLK		"mpu_free_clk"
 #define SOCFPGA_NOC_FREE_CLK		"noc_free_clk"
 #define SOCFPGA_SDMMC_FREE_CLK		"sdmmc_free_clk"
-#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw)
+#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
 
 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hw,
 					     unsigned long parent_rate)
@@ -32,7 +32,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hw,
 		div &= GENMASK(socfpgaclk->width - 1, 0);
 		div += 1;
 	} else {
-		div = ((readl(socfpgaclk->reg) & 0x7ff) + 1);
+		div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
 	}
 
 	return parent_rate / div;
@@ -43,7 +43,7 @@ static int clk_periclk_get_parent(struct clk_hw *hw)
 	struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hw);
 	u32 clk_src;
 
-	clk_src = readl(socfpgaclk->reg);
+	clk_src = readl(socfpgaclk->hw.reg);
 	if (streq(clk_hw_get_name(hw), SOCFPGA_MPU_FREE_CLK) ||
 	    streq(clk_hw_get_name(hw), SOCFPGA_NOC_FREE_CLK) ||
 	    streq(clk_hw_get_name(hw), SOCFPGA_SDMMC_FREE_CLK))
@@ -59,7 +59,7 @@ static const struct clk_ops periclk_ops = {
 };
 
 static struct clk *__socfpga_periph_init(struct device_node *node,
-	const struct clk_ops *ops)
+					 const struct clk_ops *ops)
 {
 	u32 reg;
 	struct clk_hw *hw_clk;
@@ -75,7 +75,7 @@ static struct clk *__socfpga_periph_init(struct device_node *node,
 
 	periph_clk = xzalloc(sizeof(*periph_clk));
 
-	periph_clk->reg = clk_mgr_base_addr + reg;
+	periph_clk->hw.reg = clk_mgr_base_addr + reg;
 
 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
 	if (!rc) {
@@ -101,9 +101,9 @@ static struct clk *__socfpga_periph_init(struct device_node *node,
 	init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
 	init.parent_names = parent_name;
 
-	periph_clk->hw.init = &init;
+	periph_clk->hw.hw.init = &init;
 
-	hw_clk = &periph_clk->hw;
+	hw_clk = &periph_clk->hw.hw;
 
 	rc = clk_hw_register(NULL, hw_clk);
 	if (rc)
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
index 3689b08f7d78..3f527e43f0b7 100644
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -1,4 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
+// SPDX-Comment: Origin-URL: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/socfpga/clk-periph-s10.c?id=2050b57ecda040010ec797fb07713889372c5041
 /*
  * Copyright (C) 2017, Intel Corporation
  */
@@ -15,7 +16,7 @@
 #define CLK_MGR_FREE_MASK		0x7
 #define SWCTRLBTCLKSEN_SHIFT		8
 
-#define to_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw)
+#define to_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
 
 static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
 					     unsigned long parent_rate)
@@ -23,7 +24,7 @@ static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
 	struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
 	u32 val;
 
-	val = readl(socfpgaclk->reg);
+	val = readl(socfpgaclk->hw.reg);
 	val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0);
 	parent_rate /= val;
 
@@ -39,8 +40,8 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
 	if (socfpgaclk->fixed_div) {
 		div = socfpgaclk->fixed_div;
 	} else {
-		if (socfpgaclk->reg)
-			div = ((readl(socfpgaclk->reg) & 0x7ff) + 1);
+		if (socfpgaclk->hw.reg)
+			div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
 	}
 
 	return parent_rate / div;
@@ -61,8 +62,8 @@ static int clk_periclk_get_parent(struct clk_hw *hwclk)
 			return parent;
 	}
 
-	if (socfpgaclk->reg) {
-		clk_src = readl(socfpgaclk->reg);
+	if (socfpgaclk->hw.reg) {
+		clk_src = readl(socfpgaclk->hw.reg);
 		parent = (clk_src >> CLK_MGR_FREE_SHIFT) &
 			  CLK_MGR_FREE_MASK;
 	}
@@ -90,7 +91,8 @@ struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
 	int ret;
 
 	periph_clk = xzalloc(sizeof(*periph_clk));
-	periph_clk->reg = reg + clks->offset;
+
+	periph_clk->hw.reg = reg + clks->offset;
 
 	init.name = name;
 	init.ops = &peri_c_clk_ops;
@@ -101,8 +103,8 @@ struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
 	if (init.parent_names == NULL)
 		init.parent_data = clks->parent_data;
 
-	periph_clk->hw.init = &init;
-	hw_clk = &periph_clk->hw;
+	periph_clk->hw.hw.init = &init;
+	hw_clk = &periph_clk->hw.hw;
 
 	ret = clk_hw_register(NULL, hw_clk);
 	if (ret) {
@@ -125,9 +127,9 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c
 	periph_clk = xzalloc(sizeof(*periph_clk));
 
 	if (clks->offset)
-		periph_clk->reg = regbase + clks->offset;
+		periph_clk->hw.reg = regbase + clks->offset;
 	else
-		periph_clk->reg = NULL;
+		periph_clk->hw.reg = NULL;
 
 	if (clks->bypass_reg)
 		periph_clk->bypass_reg = regbase + clks->bypass_reg;
@@ -145,8 +147,8 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c
 	if (init.parent_names == NULL)
 		init.parent_data = clks->parent_data;
 
-	periph_clk->hw.init = &init;
-	hw_clk = &periph_clk->hw;
+	periph_clk->hw.hw.init = &init;
+	hw_clk = &periph_clk->hw.hw;
 
 	ret = clk_hw_register(NULL, hw_clk);
 	if (ret) {
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index 566d99563ff6..414a5e70a5ac 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -28,7 +28,7 @@
 #define SOCFPGA_MAIN_PLL_CLK		"main_pll"
 #define SOCFPGA_PERIP_PLL_CLK		"periph_pll"
 
-#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw)
+#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
 
 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 					 unsigned long parent_rate)
@@ -38,7 +38,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 	unsigned long long vco_freq;
 
 	/* read VCO1 reg for numerator and denominator */
-	reg = readl(socfpgaclk->reg + 0x4);
+	reg = readl(socfpgaclk->hw.reg + 0x4);
 	divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
 	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
 	vco_freq = (unsigned long long)parent_rate * (divf + 1);
@@ -51,7 +51,7 @@ static int clk_pll_get_parent(struct clk_hw *hw)
 	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hw);
 	u32 pll_src;
 
-	pll_src = readl(socfpgaclk->reg);
+	pll_src = readl(socfpgaclk->hw.reg);
 
 	return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
 		CLK_MGR_PLL_CLK_SRC_MASK;
@@ -62,9 +62,9 @@ static int clk_socfpga_enable(struct clk_hw *hw)
 	struct socfpga_pll *socfpga_clk = to_socfpga_clk(hw);
 	u32 val;
 
-	val = readl(socfpga_clk->reg);
-	val |= 1 << socfpga_clk->bit_idx;
-	writel(val, socfpga_clk->reg);
+	val = readl(socfpga_clk->hw.reg);
+	val |= 1 << socfpga_clk->hw.bit_idx;
+	writel(val, socfpga_clk->hw.reg);
 
 	return 0;
 }
@@ -74,9 +74,9 @@ static void clk_socfpga_disable(struct clk_hw *hw)
 	struct socfpga_pll *socfpga_clk = to_socfpga_clk(hw);
 	u32 val;
 
-	val = readl(socfpga_clk->reg);
-	val &= ~(1 << socfpga_clk->bit_idx);
-	writel(val, socfpga_clk->reg);
+	val = readl(socfpga_clk->hw.reg);
+	val &= ~(1 << socfpga_clk->hw.bit_idx);
+	writel(val, socfpga_clk->hw.reg);
 }
 
 static struct clk_ops clk_pll_ops = {
@@ -100,7 +100,7 @@ static struct clk *__socfpga_pll_init(struct device_node *node,
 
 	pll_clk = xzalloc(sizeof(*pll_clk));
 
-	pll_clk->reg = clk_mgr_base_addr + reg;
+	pll_clk->hw.reg = clk_mgr_base_addr + reg;
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
@@ -113,18 +113,19 @@ static struct clk *__socfpga_pll_init(struct device_node *node,
 		i++;
 	init.num_parents = i;
 	init.parent_names = parent_name;
+	pll_clk->hw.hw.init = &init;
 
-	pll_clk->bit_idx = SOCFPGA_PLL_EXT_ENA;
-	hw_clk = &pll_clk->hw;
+	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
+	hw_clk = &pll_clk->hw.hw;
 
 	clk_pll_ops.enable = clk_socfpga_enable;
 	clk_pll_ops.disable = clk_socfpga_disable;
 
-	rc = clk_hw_register(NULL, &pll_clk->hw);
+	rc = clk_hw_register(NULL, &pll_clk->hw.hw);
 	if (rc)
 		ERR_PTR(rc);
 
-	return &pll_clk->hw.clk;
+	return &pll_clk->hw.hw.clk;
 }
 
 struct clk *socfpga_a10_pll_init(struct device_node *node)
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index 2b1e8f60c378..4c00c0e7481a 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -1,4 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
+// SPDX-Comment: Origin-URL: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/socfpga/clk-pll-s10.c?id=2050b57ecda040010ec797fb07713889372c5041
 /*
  * Copyright (C) 2017, Intel Corporation
  */
@@ -31,7 +32,7 @@
 
 #define SOCFPGA_BOOT_CLK		"boot_clk"
 
-#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw)
+#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
 
 static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk,
 						unsigned long parent_rate)
@@ -41,13 +42,13 @@ static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk,
 	unsigned long long vco_freq;
 
 	/* read VCO1 reg for numerator and denominator */
-	reg = readl(socfpgaclk->reg);
+	reg = readl(socfpgaclk->hw.reg);
 	arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
 
 	vco_freq = (unsigned long long)parent_rate / arefdiv;
 
 	/* Read mdiv and fdiv from the fdbck register */
-	reg = readl(socfpgaclk->reg + 0x24);
+	reg = readl(socfpgaclk->hw.reg + 0x24);
 	mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK;
 
 	vco_freq = (unsigned long long)vco_freq * mdiv;
@@ -60,7 +61,7 @@ static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
 	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
 	u32 div;
 
-	div = ((readl(socfpgaclk->reg) &
+	div = ((readl(socfpgaclk->hw.reg) &
 		SWCTRLBTCLKSEL_MASK) >>
 		SWCTRLBTCLKSEL_SHIFT);
 	div += 1;
@@ -72,7 +73,7 @@ static int clk_pll_get_parent(struct clk_hw *hwclk)
 	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
 	u32 pll_src;
 
-	pll_src = readl(socfpgaclk->reg);
+	pll_src = readl(socfpgaclk->hw.reg);
 	return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
 		CLK_MGR_PLL_CLK_SRC_MASK;
 }
@@ -82,25 +83,38 @@ static int clk_boot_get_parent(struct clk_hw *hwclk)
 	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
 	u32 pll_src;
 
-	pll_src = readl(socfpgaclk->reg);
+	pll_src = readl(socfpgaclk->hw.reg);
 	return (pll_src >> SWCTRLBTCLKSEL_SHIFT) &
 		SWCTRLBTCLKSEL_MASK;
 }
 
-/* TODO need to fix, Agilex5 SM requires change */
-static const struct clk_ops agilex5_clk_pll_ops = {
-	/* TODO This may require a custom Agilex5 implementation */
+static int clk_pll_enable(struct clk_hw *hwclk)
+{
+	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
+	u32 reg;
+
+	/* Bring PLL out of reset */
+	reg = readl(socfpgaclk->hw.reg);
+	reg |= SOCFPGA_PLL_RESET_MASK;
+	writel(reg, socfpgaclk->hw.reg);
+
+	return 0;
+}
+
+static const struct clk_ops agilex_clk_pll_ops = {
 	.recalc_rate = agilex_clk_pll_recalc_rate,
 	.get_parent = clk_pll_get_parent,
+	.enable = clk_pll_enable,
 };
 
 static const struct clk_ops clk_boot_ops = {
 	.recalc_rate = clk_boot_clk_recalc_rate,
 	.get_parent = clk_boot_get_parent,
+	.enable = clk_pll_enable,
 };
 
 struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks,
-				void __iomem *reg)
+				    void __iomem *reg)
 {
 	struct clk_hw *hw_clk;
 	struct socfpga_pll *pll_clk;
@@ -109,29 +123,27 @@ struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks,
 	int ret;
 
 	pll_clk = xzalloc(sizeof(*pll_clk));
-	pll_clk->reg = reg + clks->offset;
+
+	pll_clk->hw.reg = reg + clks->offset;
 
 	if (streq(name, SOCFPGA_BOOT_CLK))
 		init.ops = &clk_boot_ops;
 	else
-		init.ops = &agilex5_clk_pll_ops;
+		init.ops = &agilex_clk_pll_ops;
 
 	init.name = name;
 	init.flags = clks->flags;
-
 	init.num_parents = clks->num_parents;
 	init.parent_names = NULL;
 	init.parent_data = clks->parent_data;
-	pll_clk->hw.init = &init;
-
-	pll_clk->bit_idx = SOCFPGA_PLL_POWER;
-	hw_clk = &pll_clk->hw;
+	pll_clk->hw.hw.init = &init;
+	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
+	hw_clk = &pll_clk->hw.hw;
 
 	ret = clk_hw_register(NULL, hw_clk);
-	if (ret) {
-		kfree(pll_clk);
+	if (ret)
 		return ERR_PTR(ret);
-	}
+
 	return hw_clk;
 }
 
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index cc682ee4e00f..e50bdc3e20f1 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -49,14 +49,11 @@ static inline struct clk *socfpga_a10_gate_init(struct device_node *node)
 #endif
 
 struct socfpga_pll {
-	struct clk_hw hw;
-	void __iomem *reg;
-	u32 bit_idx;
-	const char *parent_names[SOCFPGA_MAX_PARENTS];
+	struct clk_gate	hw;
 };
 
 struct socfpga_gate_clk {
-	struct clk_hw hw;
+	struct clk_gate hw;
 	char *parent_name;
 	u32 fixed_div;
 	void __iomem *div_reg;
@@ -64,16 +61,11 @@ struct socfpga_gate_clk {
 	struct regmap *sys_mgr_base_addr;
 	u32 width;	/* only valid if div_reg != 0 */
 	u32 shift;	/* only valid if div_reg != 0 */
-	u32 bit_idx;
-	void __iomem *reg;
 	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
-	u32 clk_phase[2];
-	const char *parent_names[SOCFPGA_MAX_PARENTS];
 };
 
 struct socfpga_periph_clk {
-	struct clk_hw hw;
-	void __iomem *reg;
+	struct clk_gate hw;
 	char *parent_name;
 	u32 fixed_div;
 	void __iomem *div_reg;
@@ -81,7 +73,6 @@ struct socfpga_periph_clk {
 	u32 width;      /* only valid if div_reg != 0 */
 	u32 shift;      /* only valid if div_reg != 0 */
 	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
-	const char *parent_names[SOCFPGA_MAX_PARENTS];
 };
 
 #endif /* SOCFPGA_CLK_H */

-- 
2.47.3

[PATCH v2 4/4] clk: socfpga: agilex5: sync with kernel

[Michael Tretter]

From: Steffen Trumtrar <s.trumtrar@pengutronix.de>

Since v6.19-rc1 linux now has an Agilex5 clock driver [1]. This is
slightly different than the previous out-of-tree version. Sync with the
mainlined linux driver and cleanup on the way.

[1] commit 2050b57ecda040010ec797fb07713889372c5041

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/clk/socfpga/clk-agilex5.c    | 842 ++++++++++++-----------------------
 drivers/clk/socfpga/clk-gate-s10.c   |   7 +-
 drivers/clk/socfpga/clk-periph-s10.c |  38 ++
 drivers/clk/socfpga/clk-pll-s10.c    |   5 +-
 drivers/clk/socfpga/stratix10-clk.h  |  48 +-
 5 files changed, 366 insertions(+), 574 deletions(-)

diff --git a/drivers/clk/socfpga/clk-agilex5.c b/drivers/clk/socfpga/clk-agilex5.c
index f61b346ba4db..8be41920dbac 100644
--- a/drivers/clk/socfpga/clk-agilex5.c
+++ b/drivers/clk/socfpga/clk-agilex5.c
@@ -1,4 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
+// SPDX-Comment: Origin-URL: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/socfpga/clk-agilex5.c?id=2050b57ecda040010ec797fb07713889372c5041
 /*
  * Copyright (C) 2022, Intel Corporation
  */
@@ -12,506 +13,229 @@
 
 #include "stratix10-clk.h"
 
-static const struct clk_parent_data pll_mux[] = {
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+/* External parent clocks come from DT via fw_name */
+static const char * const boot_pll_parents[] = {
+	"osc1",
+	"cb-intosc-hs-div2-clk",
 };
 
-static const struct clk_parent_data boot_mux[] = {
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
+static const char * const main_pll_parents[] = {
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data core0_free_mux[] = {
-	{
-		.fw_name = "main_pll_c1",
-		.name = "main_pll_c1",
-	},
-	{
-		.fw_name = "peri_pll_c0",
-		.name = "peri_pll_c0",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const periph_pll_parents[] = {
+	"osc1",
+	"cb-intosc-hs-div2-clk",
 };
 
-static const struct clk_parent_data core1_free_mux[] = {
-	{
-		.fw_name = "main_pll_c1",
-		.name = "main_pll_c1",
-	},
-	{
-		.fw_name = "peri_pll_c0",
-		.name = "peri_pll_c0",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+/* Core free muxes */
+static const char * const core0_free_mux[] = {
+	"main_pll_c1",
+	"peri_pll_c0",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data core2_free_mux[] = {
-	{
-		.fw_name = "main_pll_c0",
-		.name = "main_pll_c0",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const core1_free_mux[] = {
+	"main_pll_c1",
+	"peri_pll_c0",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data core3_free_mux[] = {
-	{
-		.fw_name = "main_pll_c0",
-		.name = "main_pll_c0",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const core2_free_mux[] = {
+	"main_pll_c0",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data dsu_free_mux[] = {
-	{
-		.fw_name = "main_pll_c2",
-		.name = "main_pll_c2",
-	},
-	{
-		.fw_name = "peri_pll_c0",
-		.name = "peri_pll_c0",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const core3_free_mux[] = {
+	"main_pll_c0",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data noc_free_mux[] = {
-	{
-		.fw_name = "main_pll_c3",
-		.name = "main_pll_c3",
-	},
-	{
-		.fw_name = "peri_pll_c1",
-		.name = "peri_pll_c1",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const dsu_free_mux[] = {
+	"main_pll_c2",
+	"peri_pll_c0",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data emaca_free_mux[] = {
-	{
-		.fw_name = "main_pll_c1",
-		.name = "main_pll_c1",
-	},
-	{
-		.fw_name = "peri_pll_c3",
-		.name = "peri_pll_c3",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const noc_free_mux[] = {
+	"main_pll_c3",
+	"peri_pll_c1",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data emacb_free_mux[] = {
-	{
-		.fw_name = "main_pll_c1",
-		.name = "main_pll_c1",
-	},
-	{
-		.fw_name = "peri_pll_c3",
-		.name = "peri_pll_c3",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const emac_ptp_free_mux[] = {
+	"main_pll_c3",
+	"peri_pll_c3",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data emac_ptp_free_mux[] = {
-	{
-		.fw_name = "main_pll_c3",
-		.name = "main_pll_c3",
-	},
-	{
-		.fw_name = "peri_pll_c3",
-		.name = "peri_pll_c3",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const emaca_free_mux[] = {
+	"main_pll_c2",
+	"peri_pll_c3",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data gpio_db_free_mux[] = {
-	{
-		.fw_name = "main_pll_c3",
-		.name = "main_pll_c3",
-	},
-	{
-		.fw_name = "peri_pll_c1",
-		.name = "peri_pll_c1",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const emacb_free_mux[] = {
+	"main_pll_c3",
+	"peri_pll_c3",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data psi_ref_free_mux[] = {
-	{
-		.fw_name = "main_pll_c1",
-		.name = "main_pll_c1",
-	},
-	{
-		.fw_name = "peri_pll_c3",
-		.name = "peri_pll_c3",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const gpio_db_free_mux[] = {
+	"main_pll_c3",
+	"peri_pll_c1",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data usb31_free_mux[] = {
-	{
-		.fw_name = "main_pll_c3",
-		.name = "main_pll_c3",
-	},
-	{
-		.fw_name = "peri_pll_c2",
-		.name = "peri_pll_c2",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const psi_ref_free_mux[] = {
+	"main_pll_c1",
+	"peri_pll_c3",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data s2f_usr0_free_mux[] = {
-	{
-		.fw_name = "main_pll_c1",
-		.name = "main_pll_c1",
-	},
-	{
-		.fw_name = "peri_pll_c3",
-		.name = "peri_pll_c3",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const usb31_free_mux[] = {
+	"main_pll_c3",
+	"peri_pll_c2",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data s2f_usr1_free_mux[] = {
-	{
-		.fw_name = "main_pll_c1",
-		.name = "main_pll_c1",
-	},
-	{
-		.fw_name = "peri_pll_c3",
-		.name = "peri_pll_c3",
-	},
-	{
-		.fw_name = "osc1",
-		.name = "osc1",
-	},
-	{
-		.fw_name = "cb-intosc-hs-div2-clk",
-		.name = "cb-intosc-hs-div2-clk",
-	},
-	{
-		.fw_name = "f2s-free-clk",
-		.name = "f2s-free-clk",
-	},
+static const char * const s2f_user0_free_mux[] = {
+	"main_pll_c1",
+	"peri_pll_c3",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
 };
 
-static const struct clk_parent_data core0_mux[] = {
+static const char * const s2f_user1_free_mux[] = {
+	"main_pll_c1",
+	"peri_pll_c3",
+	"osc1",
+	"cb-intosc-hs-div2-clk",
+	"f2s-free-clk",
+};
+
+/* Secondary muxes between free_clk and boot_clk */
+static const char * const core0_mux[] = {
+	"core0_free_clk",
+	"boot_clk",
+};
+
+static const char * const core1_mux[] = {
+	"core1_free_clk",
+	"boot_clk",
+};
+
+static const char * const core2_mux[] = {
+	"core2_free_clk",
+	"boot_clk",
+};
+
+static const char * const core3_mux[] = {
+	"core3_free_clk",
+	"boot_clk",
+};
+
+static const char * const dsu_mux[] = {
+	"dsu_free_clk",
+	"boot_clk",
+};
+
+static const char * const noc_mux[] = {
+	"noc_free_clk",
+	"boot_clk",
+};
+
+static const char * const emac_mux[] = {
+	"emaca_free_clk",
+	"emacb_free_clk",
+	"boot_clk",
+};
+
+static const char * const s2f_user0_mux[] = {
+	"s2f_user0_free_clk",
+	"boot_clk",
+};
+
+static const char * const s2f_user1_mux[] = {
+	"s2f_user1_free_clk",
+	"boot_clk",
+};
+
+static const char * const psi_mux[] = {
+	"psi_ref_free_clk",
+	"boot_clk",
+};
+
+static const char * const gpio_db_mux[] = {
+	"gpio_db_free_clk",
+	"boot_clk",
+};
+
+static const char * const emac_ptp_mux[] = {
+	"emac_ptp_free_clk",
+	"boot_clk",
+};
+
+static const char * const usb31_mux[] = {
+	"usb31_free_clk",
+	"boot_clk",
+};
+
+static const struct agilex5_pll_clock agilex5_pll_clks[] = {
 	{
-		.fw_name = "core0_free_clk",
-		.name = "core0_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
+		.id = AGILEX5_BOOT_CLK,
 		.name = "boot_clk",
+		.parent_names = boot_pll_parents,
+		.num_parents = ARRAY_SIZE(boot_pll_parents),
+		.flags = 0,
+		.offset = 0x0,
+	},
+	{
+		.id = AGILEX5_MAIN_PLL_CLK,
+		.name = "main_pll",
+		.parent_names = main_pll_parents,
+		.num_parents = ARRAY_SIZE(main_pll_parents),
+		.flags = 0,
+		.offset = 0x48,
+	},
+	{
+		.id = AGILEX5_PERIPH_PLL_CLK,
+		.name = "periph_pll",
+		.parent_names = periph_pll_parents,
+		.num_parents = ARRAY_SIZE(periph_pll_parents),
+		.flags = 0,
+		.offset = 0x9C,
 	},
 };
 
-static const struct clk_parent_data core1_mux[] = {
-	{
-		.fw_name = "core1_free_clk",
-		.name = "core1_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data core2_mux[] = {
-	{
-		.fw_name = "core2_free_clk",
-		.name = "core2_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data core3_mux[] = {
-	{
-		.fw_name = "core3_free_clk",
-		.name = "core3_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data dsu_mux[] = {
-	{
-		.fw_name = "dsu_free_clk",
-		.name = "dsu_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data emac_mux[] = {
-	{
-		.fw_name = "emaca_free_clk",
-		.name = "emaca_free_clk",
-	},
-	{
-		.fw_name = "emacb_free_clk",
-		.name = "emacb_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data noc_mux[] = {
-	{
-		.fw_name = "noc_free_clk",
-		.name = "noc_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data s2f_user0_mux[] = {
-	{
-		.fw_name = "s2f_user0_free_clk",
-		.name = "s2f_user0_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data s2f_user1_mux[] = {
-	{
-		.fw_name = "s2f_user1_free_clk",
-		.name = "s2f_user1_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data psi_mux[] = {
-	{
-		.fw_name = "psi_ref_free_clk",
-		.name = "psi_ref_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data gpio_db_mux[] = {
-	{
-		.fw_name = "gpio_db_free_clk",
-		.name = "gpio_db_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data emac_ptp_mux[] = {
-	{
-		.fw_name = "emac_ptp_free_clk",
-		.name = "emac_ptp_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-static const struct clk_parent_data usb31_mux[] = {
-	{
-		.fw_name = "usb31_free_clk",
-		.name = "usb31_free_clk",
-	},
-	{
-		.fw_name = "boot_clk",
-		.name = "boot_clk",
-	},
-};
-
-/*
- * TODO - Clocks in AO (always on) controller
- * 2 main PLLs only
- */
-static const struct stratix10_pll_clock agilex5_pll_clks[] = {
-	{ AGILEX5_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
-	  0x0 },
-	{ AGILEX5_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux), 0,
-	  0x48 },
-	{ AGILEX5_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux), 0,
-	  0x9C },
-};
-
+/* Main PLL C0, C1, C2, C3 and Peri PLL C0, C1, C2, C3. With ping-pong counter. */
 static const struct stratix10_perip_c_clock agilex5_main_perip_c_clks[] = {
 	{ AGILEX5_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0,
 	  0x5C },
@@ -532,160 +256,153 @@ static const struct stratix10_perip_c_clock agilex5_main_perip_c_clks[] = {
 };
 
 /* Non-SW clock-gated enabled clocks */
-static const struct stratix10_perip_cnt_clock agilex5_main_perip_cnt_clks[] = {
-	{ AGILEX5_CORE0_FREE_CLK, "core0_free_clk", NULL, core0_free_mux,
-	ARRAY_SIZE(core0_free_mux), 0, 0x0104, 0, 0, 0},
-	{ AGILEX5_CORE1_FREE_CLK, "core1_free_clk", NULL, core1_free_mux,
+static const struct agilex5_perip_cnt_clock agilex5_main_perip_cnt_clks[] = {
+	{ AGILEX5_CORE0_FREE_CLK, "core0_free_clk", core0_free_mux,
+	ARRAY_SIZE(core0_free_mux), 0, 0x0100, 0, 0, 0},
+	{ AGILEX5_CORE1_FREE_CLK, "core1_free_clk", core1_free_mux,
 	ARRAY_SIZE(core1_free_mux), 0, 0x0104, 0, 0, 0},
-	{ AGILEX5_CORE2_FREE_CLK, "core2_free_clk", NULL, core2_free_mux,
+	{ AGILEX5_CORE2_FREE_CLK, "core2_free_clk", core2_free_mux,
 	ARRAY_SIZE(core2_free_mux), 0, 0x010C, 0, 0, 0},
-	{ AGILEX5_CORE3_FREE_CLK, "core3_free_clk", NULL, core3_free_mux,
+	{ AGILEX5_CORE3_FREE_CLK, "core3_free_clk", core3_free_mux,
 	ARRAY_SIZE(core3_free_mux), 0, 0x0110, 0, 0, 0},
-	{ AGILEX5_DSU_FREE_CLK, "dsu_free_clk", NULL, dsu_free_mux,
-	ARRAY_SIZE(dsu_free_mux), 0, 0x0100, 0, 0, 0},
-	{ AGILEX5_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux,
-	  ARRAY_SIZE(noc_free_mux), 0, 0x40, 0, 0, 0 },
-	{ AGILEX5_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux,
-	  ARRAY_SIZE(emaca_free_mux), 0, 0xD4, 0, 0x88, 0 },
-	{ AGILEX5_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux,
-	  ARRAY_SIZE(emacb_free_mux), 0, 0xD8, 0, 0x88, 1 },
-	{ AGILEX5_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL,
-	  emac_ptp_free_mux, ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88,
-	  2 },
-	{ AGILEX5_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
-	  ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3 },
-	{ AGILEX5_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL,
-	  s2f_usr0_free_mux, ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30,
-	  2 },
-	{ AGILEX5_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL,
-	  s2f_usr1_free_mux, ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88,
-	  5 },
-	{ AGILEX5_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
-	  ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6 },
-	{ AGILEX5_USB31_FREE_CLK, "usb31_free_clk", NULL, usb31_free_mux,
-	  ARRAY_SIZE(usb31_free_mux), 0, 0xF8, 0, 0x88, 7},
+	{ AGILEX5_DSU_FREE_CLK, "dsu_free_clk", dsu_free_mux,
+	ARRAY_SIZE(dsu_free_mux), 0, 0xfc, 0, 0, 0},
+	{ AGILEX5_NOC_FREE_CLK, "noc_free_clk", noc_free_mux,
+	ARRAY_SIZE(noc_free_mux), 0, 0x40, 0, 0, 0 },
+	{ AGILEX5_EMAC_A_FREE_CLK, "emaca_free_clk", emaca_free_mux,
+	ARRAY_SIZE(emaca_free_mux), 0, 0xD4, 0, 0x88, 0 },
+	{ AGILEX5_EMAC_B_FREE_CLK, "emacb_free_clk", emacb_free_mux,
+	ARRAY_SIZE(emacb_free_mux), 0, 0xD8, 0, 0x88, 1 },
+	{ AGILEX5_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", emac_ptp_free_mux,
+	ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2 },
+	{ AGILEX5_GPIO_DB_FREE_CLK, "gpio_db_free_clk", gpio_db_free_mux,
+	ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3 },
+	{ AGILEX5_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", s2f_user0_free_mux,
+	ARRAY_SIZE(s2f_user0_free_mux), 0, 0xE8, 0, 0x30, 2 },
+	{ AGILEX5_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", s2f_user1_free_mux,
+	ARRAY_SIZE(s2f_user1_free_mux), 0, 0xEC, 0, 0x88, 5 },
+	{ AGILEX5_PSI_REF_FREE_CLK, "psi_ref_free_clk", psi_ref_free_mux,
+	ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6 },
+	{ AGILEX5_USB31_FREE_CLK, "usb31_free_clk", usb31_free_mux,
+	ARRAY_SIZE(usb31_free_mux), 0, 0xF8, 0, 0x88, 7},
 };
 
+static const char * const cs_pdbg_parents[] = { "cs_at_clk" };
+static const char * const usb31_bus_clk_early_parents[] = { "l4_main_clk" };
+static const char * const l4_mp_clk_parent[] = { "l4_mp_clk" };
+static const char * const l4_sp_clk_parent[] = { "l4_sp_clk" };
+static const char * const dfi_clk_parent[] = { "dfi_clk" };
+
 /* SW Clock gate enabled clocks */
-static const struct stratix10_gate_clock agilex5_gate_clks[] = {
-
-	/* TODO HW Managed Clocks list */
-
-	/* TODO SW Managed Clocks list */
-
-	/* Main PLL0 Begin */
-	/* MPU clocks */
-	{ AGILEX5_CORE0_CLK, "core0_clk", NULL, core0_mux,
+static const struct agilex5_gate_clock agilex5_gate_clks[] = {
+	{ AGILEX5_CORE0_CLK, "core0_clk", core0_mux,
 	  ARRAY_SIZE(core0_mux), 0, 0x24, 8, 0, 0, 0, 0x30, 5, 0 },
-	{ AGILEX5_CORE1_CLK, "core1_clk", NULL, core1_mux,
+	{ AGILEX5_CORE1_CLK, "core1_clk", core1_mux,
 	  ARRAY_SIZE(core1_mux), 0, 0x24, 9, 0, 0, 0, 0x30, 5, 0 },
-	{ AGILEX5_CORE2_CLK, "core2_clk", NULL, core2_mux,
+	{ AGILEX5_CORE2_CLK, "core2_clk", core2_mux,
 	  ARRAY_SIZE(core2_mux), 0, 0x24, 10, 0, 0, 0, 0x30, 6, 0 },
-	{ AGILEX5_CORE3_CLK, "core3_clk", NULL, core3_mux,
+	{ AGILEX5_CORE3_CLK, "core3_clk", core3_mux,
 	  ARRAY_SIZE(core3_mux), 0, 0x24, 11, 0, 0, 0, 0x30, 7, 0 },
-	{ AGILEX5_MPU_CLK, "dsu_clk", NULL, dsu_mux, ARRAY_SIZE(dsu_mux), 0, 0,
-	  0, 0, 0, 0, 0x34, 4, 0 },
-	{ AGILEX5_MPU_PERIPH_CLK, "mpu_periph_clk", NULL, dsu_mux,
+	{ AGILEX5_MPU_CLK, "dsu_clk", dsu_mux, ARRAY_SIZE(dsu_mux), 0, 0, 0,
+	  0, 0, 0, 0x34, 4, 0 },
+	{ AGILEX5_MPU_PERIPH_CLK, "mpu_periph_clk", dsu_mux,
 	  ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 20, 2, 0x34, 4, 0 },
-	{ AGILEX5_MPU_CCU_CLK, "mpu_ccu_clk", NULL, dsu_mux,
+	{ AGILEX5_MPU_CCU_CLK, "mpu_ccu_clk", dsu_mux,
 	  ARRAY_SIZE(dsu_mux), 0, 0, 0, 0x44, 18, 2, 0x34, 4, 0 },
-
-	/* ANGTS TODO l4 main clk has no divider now. To check. */
-	{ AGILEX5_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux,
-	  ARRAY_SIZE(noc_mux), 0, 0x24, 1, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
+	{ AGILEX5_L4_MAIN_CLK, "l4_main_clk", noc_mux, ARRAY_SIZE(noc_mux),
+	  CLK_IS_CRITICAL, 0x24, 1, 0, 0, 0, 0, 0, 0 },
+	{ AGILEX5_L4_MP_CLK, "l4_mp_clk", noc_mux, ARRAY_SIZE(noc_mux), 0,
 	  0x24, 2, 0x44, 4, 2, 0x30, 1, 0 },
-	{ AGILEX5_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux,
+	{ AGILEX5_L4_SYS_FREE_CLK, "l4_sys_free_clk", noc_mux,
 	  ARRAY_SIZE(noc_mux), 0, 0, 0, 0x44, 2, 2, 0x30, 1, 0 },
-	{ AGILEX5_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
+	{ AGILEX5_L4_SP_CLK, "l4_sp_clk", noc_mux, ARRAY_SIZE(noc_mux),
 	  CLK_IS_CRITICAL, 0x24, 3, 0x44, 6, 2, 0x30, 1, 0 },
 
 	/* Core sight clocks*/
-	{ AGILEX5_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
+	{ AGILEX5_CS_AT_CLK, "cs_at_clk", noc_mux, ARRAY_SIZE(noc_mux), 0,
 	  0x24, 4, 0x44, 24, 2, 0x30, 1, 0 },
-	{ AGILEX5_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux,
+	{ AGILEX5_CS_TRACE_CLK, "cs_trace_clk", noc_mux,
 	  ARRAY_SIZE(noc_mux), 0, 0x24, 4, 0x44, 26, 2, 0x30, 1, 0 },
-	{ AGILEX5_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24, 4,
+	{ AGILEX5_CS_PDBG_CLK, "cs_pdbg_clk", cs_pdbg_parents, 1, 0, 0x24, 4,
 	  0x44, 28, 1, 0, 0, 0 },
-	/* Main PLL0 End */
 
 	/* Main Peripheral PLL1 Begin */
-	{ AGILEX5_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
+	{ AGILEX5_EMAC0_CLK, "emac0_clk", emac_mux, ARRAY_SIZE(emac_mux),
 	  0, 0x7C, 0, 0, 0, 0, 0x94, 26, 0 },
-	{ AGILEX5_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
+	{ AGILEX5_EMAC1_CLK, "emac1_clk", emac_mux, ARRAY_SIZE(emac_mux),
 	  0, 0x7C, 1, 0, 0, 0, 0x94, 27, 0 },
-	{ AGILEX5_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux),
+	{ AGILEX5_EMAC2_CLK, "emac2_clk", emac_mux, ARRAY_SIZE(emac_mux),
 	  0, 0x7C, 2, 0, 0, 0, 0x94, 28, 0 },
-	{ AGILEX5_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux,
+	{ AGILEX5_EMAC_PTP_CLK, "emac_ptp_clk", emac_ptp_mux,
 	  ARRAY_SIZE(emac_ptp_mux), 0, 0x7C, 3, 0, 0, 0, 0x88, 2, 0 },
-	{ AGILEX5_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux,
+	{ AGILEX5_GPIO_DB_CLK, "gpio_db_clk", gpio_db_mux,
 	  ARRAY_SIZE(gpio_db_mux), 0, 0x7C, 4, 0x98, 0, 16, 0x88, 3, 1 },
 	  /* Main Peripheral PLL1 End */
 
 	  /* Peripheral clocks  */
-	{ AGILEX5_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux,
+	{ AGILEX5_S2F_USER0_CLK, "s2f_user0_clk", s2f_user0_mux,
 	  ARRAY_SIZE(s2f_user0_mux), 0, 0x24, 6, 0, 0, 0, 0x30, 2, 0 },
-	{ AGILEX5_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux,
+	{ AGILEX5_S2F_USER1_CLK, "s2f_user1_clk", s2f_user1_mux,
 	  ARRAY_SIZE(s2f_user1_mux), 0, 0x7C, 6, 0, 0, 0, 0x88, 5, 0 },
-	{ AGILEX5_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux,
+	{ AGILEX5_PSI_REF_CLK, "psi_ref_clk", psi_mux,
 	  ARRAY_SIZE(psi_mux), 0, 0x7C, 7, 0, 0, 0, 0x88, 6, 0 },
-	{ AGILEX5_USB31_SUSPEND_CLK, "usb31_suspend_clk", NULL, usb31_mux,
+	{ AGILEX5_USB31_SUSPEND_CLK, "usb31_suspend_clk", usb31_mux,
 	  ARRAY_SIZE(usb31_mux), 0, 0x7C, 25, 0, 0, 0, 0x88, 7, 0 },
-	{ AGILEX5_USB31_BUS_CLK_EARLY, "usb31_bus_clk_early", "l4_main_clk",
-	  NULL, 1, 0, 0x7C, 25, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_USB2OTG_HCLK, "usb2otg_hclk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+	{ AGILEX5_USB31_BUS_CLK_EARLY, "usb31_bus_clk_early", usb31_bus_clk_early_parents,
+	  1, 0, 0x7C, 25, 0, 0, 0, 0, 0, 0 },
+	{ AGILEX5_USB2OTG_HCLK, "usb2otg_hclk", l4_mp_clk_parent, 1, 0, 0x7C,
 	  8, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_SPIM_0_CLK, "spim_0_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 9,
+	{ AGILEX5_SPIM_0_CLK, "spim_0_clk", l4_mp_clk_parent, 1, 0, 0x7C, 9,
 	  0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_SPIM_1_CLK, "spim_1_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 11,
+	{ AGILEX5_SPIM_1_CLK, "spim_1_clk", l4_mp_clk_parent, 1, 0, 0x7C, 11,
 	  0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_SPIS_0_CLK, "spis_0_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 12,
+	{ AGILEX5_SPIS_0_CLK, "spis_0_clk", l4_sp_clk_parent, 1, 0, 0x7C, 12,
 	  0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_SPIS_1_CLK, "spis_1_clk", "l4_sp_clk", NULL, 1, 0, 0x7C, 13,
+	{ AGILEX5_SPIS_1_CLK, "spis_1_clk", l4_sp_clk_parent, 1, 0, 0x7C, 13,
 	  0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_DMA_CORE_CLK, "dma_core_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+	{ AGILEX5_DMA_CORE_CLK, "dma_core_clk", l4_mp_clk_parent, 1, 0, 0x7C,
 	  14, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_DMA_HS_CLK, "dma_hs_clk", "l4_mp_clk", NULL, 1, 0, 0x7C, 14,
+	{ AGILEX5_DMA_HS_CLK, "dma_hs_clk", l4_mp_clk_parent, 1, 0, 0x7C, 14,
 	  0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_I3C_0_CORE_CLK, "i3c_0_core_clk", "l4_mp_clk", NULL, 1, 0,
+	{ AGILEX5_I3C_0_CORE_CLK, "i3c_0_core_clk", l4_mp_clk_parent, 1, 0,
 	  0x7C, 18, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_I3C_1_CORE_CLK, "i3c_1_core_clk", "l4_mp_clk", NULL, 1, 0,
+	{ AGILEX5_I3C_1_CORE_CLK, "i3c_1_core_clk", l4_mp_clk_parent, 1, 0,
 	  0x7C, 19, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_I2C_0_PCLK, "i2c_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 15,
+	{ AGILEX5_I2C_0_PCLK, "i2c_0_pclk", l4_sp_clk_parent, 1, 0, 0x7C, 15,
 	  0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_I2C_1_PCLK, "i2c_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 16,
+	{ AGILEX5_I2C_1_PCLK, "i2c_1_pclk", l4_sp_clk_parent, 1, 0, 0x7C, 16,
 	  0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_I2C_EMAC0_PCLK, "i2c_emac0_pclk", "l4_sp_clk", NULL, 1, 0,
+	{ AGILEX5_I2C_EMAC0_PCLK, "i2c_emac0_pclk", l4_sp_clk_parent, 1, 0,
 	  0x7C, 17, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_I2C_EMAC1_PCLK, "i2c_emac1_pclk", "l4_sp_clk", NULL, 1, 0,
+	{ AGILEX5_I2C_EMAC1_PCLK, "i2c_emac1_pclk", l4_sp_clk_parent, 1, 0,
 	  0x7C, 22, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_I2C_EMAC2_PCLK, "i2c_emac2_pclk", "l4_sp_clk", NULL, 1, 0,
+	{ AGILEX5_I2C_EMAC2_PCLK, "i2c_emac2_pclk", l4_sp_clk_parent, 1, 0,
 	  0x7C, 27, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_UART_0_PCLK, "uart_0_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 20,
+	{ AGILEX5_UART_0_PCLK, "uart_0_pclk", l4_sp_clk_parent, 1, 0, 0x7C, 20,
 	  0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_UART_1_PCLK, "uart_1_pclk", "l4_sp_clk", NULL, 1, 0, 0x7C, 21,
+	{ AGILEX5_UART_1_PCLK, "uart_1_pclk", l4_sp_clk_parent, 1, 0, 0x7C, 21,
 	  0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_SPTIMER_0_PCLK, "sptimer_0_pclk", "l4_sp_clk", NULL, 1, 0,
+	{ AGILEX5_SPTIMER_0_PCLK, "sptimer_0_pclk", l4_sp_clk_parent, 1, 0,
 	  0x7C, 23, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_SPTIMER_1_PCLK, "sptimer_1_pclk", "l4_sp_clk", NULL, 1, 0,
+	{ AGILEX5_SPTIMER_1_PCLK, "sptimer_1_pclk", l4_sp_clk_parent, 1, 0,
 	  0x7C, 24, 0, 0, 0, 0, 0, 0 },
 
 	/*NAND, SD/MMC and SoftPHY overall clocking*/
-	{ AGILEX5_DFI_CLK, "dfi_clk", "l4_mp_clk", NULL, 1, 0, 0, 0, 0x44, 16,
+	{ AGILEX5_DFI_CLK, "dfi_clk", l4_mp_clk_parent, 1, 0, 0, 0, 0x44, 16,
 	  2, 0, 0, 0 },
-	{ AGILEX5_NAND_NF_CLK, "nand_nf_clk", "dfi_clk", NULL, 1, 0, 0x7C, 10,
+	{ AGILEX5_NAND_NF_CLK, "nand_nf_clk", dfi_clk_parent, 1, 0, 0x7C, 10,
 	  0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_NAND_BCH_CLK, "nand_bch_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
+	{ AGILEX5_NAND_BCH_CLK, "nand_bch_clk", l4_mp_clk_parent, 1, 0, 0x7C,
 	  10, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_SDMMC_SDPHY_REG_CLK, "sdmmc_sdphy_reg_clk", "l4_mp_clk", NULL,
+	{ AGILEX5_SDMMC_SDPHY_REG_CLK, "sdmmc_sdphy_reg_clk", l4_mp_clk_parent,
 	  1, 0, 0x7C, 5, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_SDMCLK, "sdmclk", "dfi_clk", NULL, 1, 0, 0x7C, 5, 0, 0, 0, 0,
-	  0, 0 },
-	{ AGILEX5_SOFTPHY_REG_PCLK, "softphy_reg_pclk", "l4_mp_clk", NULL, 1, 0,
+	{ AGILEX5_SDMCLK, "sdmclk", dfi_clk_parent, 1, 0, 0x7C, 5, 0, 0, 0,
+	  0, 0, 0 },
+	{ AGILEX5_SOFTPHY_REG_PCLK, "softphy_reg_pclk", l4_mp_clk_parent, 1, 0,
 	  0x7C, 26, 0, 0, 0, 0, 0, 0 },
-	{ AGILEX5_SOFTPHY_PHY_CLK, "softphy_phy_clk", "l4_mp_clk", NULL, 1, 0,
+	{ AGILEX5_SOFTPHY_PHY_CLK, "softphy_phy_clk", l4_mp_clk_parent, 1, 0,
 	  0x7C, 26, 0x44, 16, 2, 0, 0, 0 },
-	{ AGILEX5_SOFTPHY_CTRL_CLK, "softphy_ctrl_clk", "dfi_clk", NULL, 1, 0,
+	{ AGILEX5_SOFTPHY_CTRL_CLK, "softphy_ctrl_clk", dfi_clk_parent, 1, 0,
 	  0x7C, 26, 0, 0, 0, 0, 0, 0 },
 };
 
@@ -710,7 +427,7 @@ agilex5_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
 }
 
 static int
-agilex5_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
+agilex5_clk_register_cnt_perip(const struct agilex5_perip_cnt_clock *clks,
 			       int nums, struct stratix10_clock_data *data)
 {
 	struct clk_hw *hw_clk;
@@ -718,7 +435,7 @@ agilex5_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
 	int i;
 
 	for (i = 0; i < nums; i++) {
-		hw_clk = s10_register_cnt_periph(&clks[i], base);
+		hw_clk = agilex5_register_cnt_periph(&clks[i], base);
 		if (IS_ERR(hw_clk)) {
 			pr_err("%s: failed to register clock %s\n", __func__,
 			       clks[i].name);
@@ -730,7 +447,7 @@ agilex5_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
 	return 0;
 }
 
-static int agilex5_clk_register_gate(const struct stratix10_gate_clock *clks,
+static int agilex5_clk_register_gate(const struct agilex5_gate_clock *clks,
 				     int nums,
 				     struct stratix10_clock_data *data)
 {
@@ -739,7 +456,7 @@ static int agilex5_clk_register_gate(const struct stratix10_gate_clock *clks,
 	int i;
 
 	for (i = 0; i < nums; i++) {
-		hw_clk = agilex_register_gate(&clks[i], base);
+		hw_clk = agilex5_register_gate(&clks[i], base);
 		if (IS_ERR(hw_clk)) {
 			pr_err("%s: failed to register clock %s\n", __func__,
 			       clks[i].name);
@@ -751,7 +468,7 @@ static int agilex5_clk_register_gate(const struct stratix10_gate_clock *clks,
 	return 0;
 }
 
-static int agilex5_clk_register_pll(const struct stratix10_pll_clock *clks,
+static int agilex5_clk_register_pll(const struct agilex5_pll_clock *clks,
 				    int nums, struct stratix10_clock_data *data)
 {
 	struct clk_hw *hw_clk;
@@ -797,6 +514,7 @@ static int agilex5_clkmgr_probe(struct device *dev)
 	agilex5_clk_register_pll(agilex5_pll_clks, ARRAY_SIZE(agilex5_pll_clks),
 				 clk_data);
 
+	/* mainPLL C0, C1, C2, C3 and periph PLL C0, C1, C2, C3*/
 	agilex5_clk_register_c_perip(agilex5_main_perip_c_clks,
 				     ARRAY_SIZE(agilex5_main_perip_c_clks),
 				     clk_data);
diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c
index 8fc8a4ea7b8f..fc803b69a2a0 100644
--- a/drivers/clk/socfpga/clk-gate-s10.c
+++ b/drivers/clk/socfpga/clk-gate-s10.c
@@ -124,12 +124,11 @@ static const struct clk_ops dbgclk_ops = {
 	.get_parent = socfpga_gate_get_parent,
 };
 
-struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
+struct clk_hw *agilex5_register_gate(const struct agilex5_gate_clock *clks, void __iomem *regbase)
 {
 	struct clk_hw *hw_clk;
 	struct socfpga_gate_clk *socfpga_clk;
 	struct clk_init_data init;
-	const char *parent_name = clks->parent_name;
 	int ret;
 
 	socfpga_clk = xzalloc(sizeof(*socfpga_clk));
@@ -161,9 +160,7 @@ struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, voi
 	init.name = clks->name;
 	init.flags = clks->flags;
 	init.num_parents = clks->num_parents;
-	init.parent_names = parent_name ? &parent_name : NULL;
-	if (init.parent_names == NULL)
-		init.parent_data = clks->parent_data;
+	init.parent_names = clks->parent_names;
 	socfpga_clk->hw.hw.init = &init;
 	hw_clk = &socfpga_clk->hw.hw;
 
diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
index 3f527e43f0b7..4c3184b92fbe 100644
--- a/drivers/clk/socfpga/clk-periph-s10.c
+++ b/drivers/clk/socfpga/clk-periph-s10.c
@@ -157,3 +157,41 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c
 	}
 	return hw_clk;
 }
+
+struct clk_hw *agilex5_register_cnt_periph(const struct agilex5_perip_cnt_clock *clks,
+					   void __iomem *regbase)
+{
+	struct clk_hw *hw_clk;
+	struct socfpga_periph_clk *periph_clk;
+	struct clk_init_data init;
+	const char *name = clks->name;
+	int ret;
+
+	periph_clk = xzalloc(sizeof(*periph_clk));
+
+	if (clks->offset)
+		periph_clk->hw.reg = regbase + clks->offset;
+	else
+		periph_clk->hw.reg = NULL;
+
+	if (clks->bypass_reg)
+		periph_clk->bypass_reg = regbase + clks->bypass_reg;
+	else
+		periph_clk->bypass_reg = NULL;
+	periph_clk->bypass_shift = clks->bypass_shift;
+	periph_clk->fixed_div = clks->fixed_divider;
+
+	init.name = name;
+	init.ops = &peri_cnt_clk_ops;
+	init.flags = clks->flags;
+	init.num_parents = clks->num_parents;
+	init.parent_names = clks->parent_names;
+	periph_clk->hw.hw.init = &init;
+	hw_clk = &periph_clk->hw.hw;
+
+	ret = clk_hw_register(NULL, hw_clk);
+	if (ret)
+		return ERR_PTR(ret);
+
+	return hw_clk;
+}
diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c
index 4c00c0e7481a..be07d735181e 100644
--- a/drivers/clk/socfpga/clk-pll-s10.c
+++ b/drivers/clk/socfpga/clk-pll-s10.c
@@ -113,7 +113,7 @@ static const struct clk_ops clk_boot_ops = {
 	.enable = clk_pll_enable,
 };
 
-struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks,
+struct clk_hw *agilex5_register_pll(const struct agilex5_pll_clock *clks,
 				    void __iomem *reg)
 {
 	struct clk_hw *hw_clk;
@@ -134,8 +134,7 @@ struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks,
 	init.name = name;
 	init.flags = clks->flags;
 	init.num_parents = clks->num_parents;
-	init.parent_names = NULL;
-	init.parent_data = clks->parent_data;
+	init.parent_names = clks->parent_names;
 	pll_clk->hw.hw.init = &init;
 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
 	hw_clk = &pll_clk->hw.hw;
diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
index 1fe025f65f7a..bd13424e8557 100644
--- a/drivers/clk/socfpga/stratix10-clk.h
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -1,4 +1,5 @@
 /* SPDX-License-Identifier:    GPL-2.0 */
+/* SPDX-Comment: Origin-URL: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/socfpga/stratix10-clk.h?id=2050b57ecda040010ec797fb07713889372c5041 */
 /*
  * Copyright (C) 2017, Intel Corporation
  */
@@ -62,12 +63,51 @@ struct stratix10_gate_clock {
 	u8			fixed_div;
 };
 
-struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks,
-				void __iomem *reg);
+struct agilex5_pll_clock {
+	unsigned int	id;
+	const char	*name;
+	const char	* const *parent_names;
+	u8	num_parents;
+	unsigned long   flags;
+	unsigned long   offset;
+};
+
+struct agilex5_perip_cnt_clock {
+	unsigned int		id;
+	const char		*name;
+	const char	* const *parent_names;
+	u8			num_parents;
+	unsigned long		flags;
+	unsigned long		offset;
+	u8			fixed_divider;
+	unsigned long		bypass_reg;
+	unsigned long		bypass_shift;
+};
+
+struct agilex5_gate_clock {
+	unsigned int		id;
+	const char		*name;
+	const char	* const *parent_names;
+	u8			num_parents;
+	unsigned long		flags;
+	unsigned long		gate_reg;
+	u8			gate_idx;
+	unsigned long		div_reg;
+	u8			div_offset;
+	u8			div_width;
+	unsigned long		bypass_reg;
+	u8			bypass_shift;
+	u8			fixed_div;
+};
+
+struct clk_hw *agilex5_register_pll(const struct agilex5_pll_clock *clks,
+				    void __iomem *reg);
+struct clk_hw *agilex5_register_cnt_periph(const struct agilex5_perip_cnt_clock *clks,
+					   void __iomem *regbase);
+struct clk_hw *agilex5_register_gate(const struct agilex5_gate_clock *clks,
+				     void __iomem *regbase);
 struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
 				void __iomem *reg);
 struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
 				    void __iomem *reg);
-struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks,
-			      void __iomem *reg);
 #endif	/* __STRATIX10_CLK_H */

-- 
2.47.3