[PATCH master v2 0/5] ARM64: unify pbl and proper malloc area start

[PATCH master v2 0/5] ARM64: unify pbl and proper malloc area start

[Ahmad Fatoum]

The current location used to place the very early PBL malloc area on
Rockchip overlaps the OP-TEE region. This series changes ARM64 to
make the start of the barebox proper malloc area easier to calculate and
uses that also for the PBL memory region.

v1: https://lore.barebox.org/barebox/20260522105852.2681680-1-a.fatoum@pengutronix.de/

v1 -> v2:
  - restrict to ARM64 only
  - make the offset from start of RAM instead of end (Sascha)

Ahmad Fatoum (5):
  arch: introduce new CONFIG_ARCH_HAS_MALLOC_SIZE
  arch: introduce CONFIG_BAREBOX_MEMORY_OFFSET
  ARM64: switch to CONFIG_BAREBOX_MEMORY_OFFSET
  ARM64: configs: drop CONFIG_MALLOC_SIZE=0x0 as it's now the default
  ARM64: place PBL malloc area at start of barebox proper malloc area

 arch/Kconfig                               | 19 ++++++++++
 arch/arm/Kconfig                           |  2 +
 arch/arm/configs/efi_v8_defconfig          |  1 -
 arch/arm/configs/imx_v8_defconfig          |  1 -
 arch/arm/configs/layerscape_defconfig      |  1 -
 arch/arm/configs/multi_v8_defconfig        |  1 -
 arch/arm/configs/rockchip_v8_defconfig     |  1 -
 arch/arm/configs/rpi_v8a_defconfig         |  3 +-
 arch/arm/configs/socfpga-agilex5_defconfig |  1 -
 arch/arm/configs/zynqmp_defconfig          |  1 -
 arch/arm/cpu/common.c                      |  5 +++
 arch/arm/cpu/start.c                       | 10 +++++
 arch/arm/cpu/uncompress.c                  |  4 ++
 arch/arm/include/asm/barebox-arm.h         | 10 +++--
 arch/arm/mach-rockchip/atf.c               |  2 +-
 arch/mips/Kconfig                          |  1 +
 arch/openrisc/Kconfig                      |  1 +
 arch/powerpc/Kconfig                       |  1 +
 arch/riscv/Kconfig                         |  1 +
 arch/sandbox/Kconfig                       |  1 +
 common/Kconfig                             | 43 +++++++++++++++++++++-
 common/memory.c                            |  7 ++++
 include/asm-generic/memory_layout.h        | 24 ++++++++++++
 include/linux/pagemap.h                    |  1 +
 24 files changed, 126 insertions(+), 16 deletions(-)

-- 
2.47.3

[PATCH master v2 1/5] arch: introduce new CONFIG_ARCH_HAS_MALLOC_SIZE

[Ahmad Fatoum]

The new option is selected for all platforms, except for x86 and kvx as
these two platforms are the only ones that do not use MALLOC_SIZE:

- x86 (EFI payload): always allocates 16M as all bigger allocations
  are serviced via calling into the UEFI firmware.

- kvx always initializes memory area from barebox_text_end to end of
  memory described in DT

Note that CONFIG_MALLOC_SIZE is not hidden when ARCH_HAS_MALLOC_SIZE
is not selected. The reason for that is that CONFIG_MALLOC_SIZE is most
often 0 (malloc area is dynamically determined), but the Kconfig default
is 4M. This would lead to a breakage when bisecting for most boards:

- Board has CONFIG_MALLOC_SIZE=0
- Bisect jumps over commit removing ARCH_HAS_MALLOC_SIZE for an arch
- CONFIG_MALLOC_SIZE is set to default SZ_4M

This can easily happen, so we keep CONFIG_MALLOC_SIZE around even when
the symbol is unset at a value of 0 to cover the most common case.

For boards that actually set a non-zero value, special consideration
may need to be taken on bisect if the dynamic determination is not
sufficient.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/Kconfig            | 6 ++++++
 arch/arm/Kconfig        | 1 +
 arch/mips/Kconfig       | 1 +
 arch/openrisc/Kconfig   | 1 +
 arch/powerpc/Kconfig    | 1 +
 arch/riscv/Kconfig      | 1 +
 arch/sandbox/Kconfig    | 1 +
 common/Kconfig          | 5 +++--
 common/memory.c         | 3 +++
 include/linux/pagemap.h | 1 +
 10 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index 9f5673b5da31..23e65d58d52b 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -92,6 +92,12 @@ config ARCH_HAS_DATA_ABORT_MASK_PBL
 config ARCH_HAS_ZERO_PAGE
 	bool
 
+config ARCH_HAS_MALLOC_SIZE
+	bool
+	help
+	  This is selected by architectures, where CONFIG_MALLOC_SIZE
+	  can be used to specify an exact size of the malloc area.
+
 config HAVE_EFFICIENT_UNALIGNED_ACCESS
 	bool
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c735a0dbfd5b..53bddd55e179 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -20,6 +20,7 @@ config ARM
 	select ARCH_HAS_DMA_WRITE_COMBINE
 	select HAVE_EFI_LOADER if MMU # for payload unaligned accesses
 	select PBL_IMAGE_ELF
+	select ARCH_HAS_MALLOC_SIZE
 	default y
 
 config ARCH_LINUX_NAME
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d34377a33d47..264815f34d06 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -14,6 +14,7 @@ config MIPS
 	select ARCH_HAS_SJLJ
 	select ELF
 	select HAVE_ARCH_BOOTM_OFTREE
+	select ARCH_HAS_MALLOC_SIZE
 	default y
 
 config ARCH_LINUX_NAME
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index f82d160a3a15..c81be0aa8019 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -8,6 +8,7 @@ config OPENRISC
 	select GENERIC_FIND_NEXT_BIT
 	select ARCH_HAS_SJLJ
 	select HAS_DEBUG_LL
+	select ARCH_HAS_MALLOC_SIZE
 	default y
 
 config ARCH_MKIMAGE_NAME
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 49050a26d524..d9c9f3583463 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -9,6 +9,7 @@ config PPC
 	select OFTREE
 	select HAVE_ARCH_BOOTM_OFTREE
 	select ARCH_HAS_SJLJ
+	select ARCH_HAS_MALLOC_SIZE
 	default y
 
 config ARCH_LINUX_NAME
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f1d98d1b33a5..3e5de8e0ec63 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -21,6 +21,7 @@ config RISCV
 	select PBL_IMAGE_ELF
 	select HAVE_ARCH_BOARD_GENERIC_DT
 	select HAVE_ARCH_BOOTM_OFTREE
+	select ARCH_HAS_MALLOC_SIZE
 
 config ARCH_LINUX_NAME
 	string
diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index 504171809193..07821738f27a 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -27,6 +27,7 @@ config SANDBOX
 	select HAVE_PBL_MULTI_IMAGES
 	select PBL_IMAGE_NO_PIGGY
 	select PBL_CLOCKSOURCE if COMPILE_TEST
+	select ARCH_HAS_MALLOC_SIZE
 	default y
 
 config ARCH_LINUX_NAME
diff --git a/common/Kconfig b/common/Kconfig
index bfca650c49cc..1b2f12498355 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -296,8 +296,9 @@ config MALLOC_BASE
 
 config MALLOC_SIZE
 	hex
-	default 0x400000
-	prompt "malloc area size"
+	default 0x400000 if ARCH_HAS_MALLOC_SIZE
+	default 0
+	prompt "malloc area size" if ARCH_HAS_MALLOC_SIZE
 
 config SCRATCH_SIZE
 	hex
diff --git a/common/memory.c b/common/memory.c
index b61df68e02dc..bf927b6a30f3 100644
--- a/common/memory.c
+++ b/common/memory.c
@@ -12,6 +12,7 @@
 #include <init.h>
 #include <linux/ioport.h>
 #include <linux/err.h>
+#include <linux/pagemap.h>
 #include <asm-generic/memory_layout.h>
 #include <asm/sections.h>
 #include <malloc.h>
@@ -53,6 +54,8 @@ void mem_malloc_init(void *start, void *end)
 	mem_malloc_initialized = 1;
 }
 
+static_assert(PAGE_ALIGNED(CONFIG_MALLOC_SIZE));
+
 static struct resource *barebox_res;
 static resource_size_t barebox_start;
 static resource_size_t barebox_size;
diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h
index 8bdaff4ebf1b..2ca8464f5092 100644
--- a/include/linux/pagemap.h
+++ b/include/linux/pagemap.h
@@ -15,6 +15,7 @@
 #define PAGE_MASK	(PAGE_SIZE - 1)
 #define PAGE_ALIGN(s)	ALIGN(s, PAGE_SIZE)
 #define PAGE_ALIGN_DOWN(x) ALIGN_DOWN(x, PAGE_SIZE)
+#define PAGE_ALIGNED(addr)  IS_ALIGNED((unsigned long)(addr), PAGE_SIZE)
 
 #define PAGE_CACHE_SHIFT        PAGE_SHIFT
 #define PAGE_CACHE_SIZE         PAGE_SIZE
-- 
2.47.3

[PATCH master v2 2/5] arch: introduce CONFIG_BAREBOX_MEMORY_OFFSET

[Ahmad Fatoum]

With barebox proper placed at end of RAM, the current CONFIG_MALLOC_SIZE
puts us into a tight spot: We must determine the size barebox proper
will occupy to subtract CONFIG_MALLOC_SIZE from it, but we may not know
the size yet in early stages of PBL, especially when we have separate
first and second stages.

This complexity in calculation is imposed onto all users, even though
most users probably don't make use of CONFIG_MALLOC_SIZE and set it to
zero anyway to let barebox compute a suitable malloc area size.

CONFIG_BAREBOX_MEMORY_OFFSET simplifies calculation by starting the
malloc area at the specified offset from start of RAM.

Boards that used to set CONFIG_MALLOC_SIZE will need to set the new
CONFIG_BAREBOX_MEMORY_OFFSET, e.g. by converting the old
CONFIG_MALLOC_SIZE value:

 initial memory_size - old CONFIG_MALLOC_SIZE
   - the area barebox occupies at end of initial memory

For all other boards, they can just keep the default of
CONFIG_BAREBOX_MEMORY_OFFSET=0 and barebox will start the malloc area at
half of RAM or 1G before end, whichever is smaller.

This computation is independent of barebox size and can thus be used in
early PBL as well in a later commit.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/Kconfig                        | 13 ++++++++++
 common/Kconfig                      | 38 +++++++++++++++++++++++++++++
 common/memory.c                     |  4 +++
 include/asm-generic/memory_layout.h | 24 ++++++++++++++++++
 4 files changed, 79 insertions(+)

diff --git a/arch/Kconfig b/arch/Kconfig
index 23e65d58d52b..b4fe34aa9760 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -98,6 +98,19 @@ config ARCH_HAS_MALLOC_SIZE
 	  This is selected by architectures, where CONFIG_MALLOC_SIZE
 	  can be used to specify an exact size of the malloc area.
 
+	  Eventually, this should only be selected by sandbox, with
+	  everyone else switched over to ARCH_HAS_BAREBOX_MEMORY_OFFSET.
+
+config ARCH_HAS_BAREBOX_MEMORY_OFFSET
+	bool
+	help
+	  This is selected by architectures, where CONFIG_BAREBOX_MEMORY_OFFSET
+	  can be used to specify the start offset of the barebox memory
+	  within the initially available memory (first memory bank usually).
+
+	  Compared to CONFIG_MALLOC_SIZE, this offset simplifies memory layout
+	  calculation and allows to reserve the malloc region very early on.
+
 config HAVE_EFFICIENT_UNALIGNED_ACCESS
 	bool
 
diff --git a/common/Kconfig b/common/Kconfig
index 1b2f12498355..f9985d8aa4b5 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -300,6 +300,44 @@ config MALLOC_SIZE
 	default 0
 	prompt "malloc area size" if ARCH_HAS_MALLOC_SIZE
 
+config BAREBOX_MEMORY_OFFSET
+	hex
+	default 0
+	prompt "relative malloc base offset (optional)"
+	depends on ARCH_HAS_BAREBOX_MEMORY_OFFSET
+	help
+	  Most boards should just leave this at the default zero and barebox
+	  will dynamically determine the offset, from the start of the initial
+	  memory bank in DRAM, at which the barebox runtime region begins.
+
+	  Memory below this offset is reserved as the OS load region, used for
+	  placement of the kernel, initrd and device tree before boot.
+
+	  barebox itself, the relocated binary, BSS, stack and malloc area
+	  all live at and above this offset and will not allocate into the
+	  OS load region.
+
+	  When set to zero, following heuristic will be used:
+
+	    - If the prebootloader reports 2GiB of initial memory or more,
+	      start the barebox runtime region at offset 1GiB from
+	      start of initial memory.
+
+	    - Otherwise, start the barebox runtimer region right in the
+	      middle of the initial memory region.
+
+          This heuristic should be suitable for most boards with modern DRAM
+	  sizes. If you run into problems with it, adapt this option, so
+          it is large enough to hold the biggest OS image you expect to boot,
+	  plus initramfs and DTB.
+
+	  Note that this affects only the split in the initial memory reported
+	  by the bootloader. Placement of final boot artifacts can happen
+	  outside of the malloc area and are not restricted to this initial
+	  memory or even the first SDRAM bank.
+
+	  If unsure, keep the default of 0x0.
+
 config SCRATCH_SIZE
 	hex
 	default 0x8000
diff --git a/common/memory.c b/common/memory.c
index bf927b6a30f3..e436707cf8da 100644
--- a/common/memory.c
+++ b/common/memory.c
@@ -56,6 +56,10 @@ void mem_malloc_init(void *start, void *end)
 
 static_assert(PAGE_ALIGNED(CONFIG_MALLOC_SIZE));
 
+#ifdef CONFIG_BAREBOX_MEMORY_OFFSET
+static_assert(PAGE_ALIGNED(CONFIG_BAREBOX_MEMORY_OFFSET));
+#endif
+
 static struct resource *barebox_res;
 static resource_size_t barebox_start;
 static resource_size_t barebox_size;
diff --git a/include/asm-generic/memory_layout.h b/include/asm-generic/memory_layout.h
index d477f7bbdbf7..1df7aec18739 100644
--- a/include/asm-generic/memory_layout.h
+++ b/include/asm-generic/memory_layout.h
@@ -36,6 +36,12 @@
 #define STACK_SIZE  CONFIG_STACK_SIZE
 #define SCRATCH_SIZE	CONFIG_SCRATCH_SIZE
 
+#ifndef __ASSEMBLY__
+
+#include <linux/pagemap.h>
+#include <linux/minmax.h>
+#include <linux/sizes.h>
+
 /*
  * This generates a useless load from the specified symbol
  * to ensure linker garbage collection doesn't delete it
@@ -43,4 +49,22 @@
 #define __keep_symbolref(sym)	\
 	__asm__ __volatile__("": :"r"(&sym) :)
 
+#ifdef CONFIG_BAREBOX_MEMORY_OFFSET
+static inline unsigned long barebox_malloc_base(unsigned long membase,
+						unsigned long memsize)
+ {
+	 unsigned long offset = CONFIG_BAREBOX_MEMORY_OFFSET;
+
+	 if (offset >= memsize)
+		 offset = 0;
+
+	 if (!offset)
+		 offset = memsize - min_t(unsigned long, memsize / 2, SZ_1G);
+
+	 return PAGE_ALIGN(membase + offset);
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* __ASM_GENERIC_MEMORY_LAYOUT_H */
-- 
2.47.3

[PATCH master v2 3/5] ARM64: switch to CONFIG_BAREBOX_MEMORY_OFFSET

[Ahmad Fatoum]

In preparation for using the barebox proper malloc area in PBL too,
switch over ARM64 to CONFIG_BAREBOX_MEMORY_OFFSET as this allows
calculating the malloc area start without needing to know the eventual
size of barebox proper itself.

The switch for ARM32 is more involved, so that's omitted for now without
a comment explaining why. Once we have migrated the xload code to not
use the malloc area for second stage placement and weeded out the
bugs[1], we should be good to go[1].

[1]: On a Beagle Bone Black, despite first stage being moved out of
malloc area, I get a data abort before barebox_pbl_start...

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/Kconfig     |  3 ++-
 arch/arm/cpu/start.c | 10 ++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 53bddd55e179..c7a883338b0b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -20,7 +20,6 @@ config ARM
 	select ARCH_HAS_DMA_WRITE_COMBINE
 	select HAVE_EFI_LOADER if MMU # for payload unaligned accesses
 	select PBL_IMAGE_ELF
-	select ARCH_HAS_MALLOC_SIZE
 	default y
 
 config ARCH_LINUX_NAME
@@ -34,10 +33,12 @@ config ARCH_MKIMAGE_NAME
 
 config ARM32
 	def_bool CPU_32
+	select ARCH_HAS_MALLOC_SIZE
 
 config ARM64
 	def_bool CPU_64
 	select ARCH_HAS_RELR
+	select ARCH_HAS_BAREBOX_MEMORY_OFFSET
 
 config ARCH_TEXT_BASE
 	hex
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index bbcf465be4db..6a9941275c12 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -156,6 +156,15 @@ __noreturn void barebox_non_pbl_start(unsigned long membase,
 		armv7r_mpu_init_coherent(malloc_end, REGION_8MB);
 	}
 
+#ifdef CONFIG_ARM64
+	malloc_start = barebox_malloc_base(membase, memsize);
+#else
+	/* TODO: migrate ARM32 to barebox_malloc_base(), once legacy xload
+	 * code has been migrated to loadables; On boards like the beaglebone,
+	 * a separate first stage barebox loads the second stage into RAM
+	 * and executes it from there, so reusing the malloc area in second
+	 * stage PBL will mangle the second stage code.
+	 */
 	/*
 	 * Maximum malloc space is the Kconfig value if given
 	 * or 1GB.
@@ -169,6 +178,7 @@ __noreturn void barebox_non_pbl_start(unsigned long membase,
 		if (malloc_end - malloc_start > SZ_1G)
 			malloc_start = malloc_end - SZ_1G;
 	}
+#endif
 
 	pr_debug("initializing malloc pool at 0x%08lx (size 0x%08lx)\n",
 			malloc_start, malloc_end - malloc_start);
-- 
2.47.3

[PATCH master v2 4/5] ARM64: configs: drop CONFIG_MALLOC_SIZE=0x0 as it's now the default

[Ahmad Fatoum]

CONFIG_MALLOC_SIZE=0x0 is not the default value, although it's the most
commonly used. We couldn't turn around and change this now without
breakage.

CONFIG_BAREBOX_MEMORY_OFFSET=0x0 behaves the same as CONFIG_MALLOC_SIZE=0x0
and is the default, so we can drop CONFIG_MALLOC_SIZE=0x0 now.

No functional change.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/configs/efi_v8_defconfig          | 1 -
 arch/arm/configs/imx_v8_defconfig          | 1 -
 arch/arm/configs/layerscape_defconfig      | 1 -
 arch/arm/configs/multi_v8_defconfig        | 1 -
 arch/arm/configs/rockchip_v8_defconfig     | 1 -
 arch/arm/configs/rpi_v8a_defconfig         | 3 +--
 arch/arm/configs/socfpga-agilex5_defconfig | 1 -
 arch/arm/configs/zynqmp_defconfig          | 1 -
 8 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/arch/arm/configs/efi_v8_defconfig b/arch/arm/configs/efi_v8_defconfig
index 5f946dd51d4a..51eaad78a11e 100644
--- a/arch/arm/configs/efi_v8_defconfig
+++ b/arch/arm/configs/efi_v8_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_PSCI_CLIENT=y
 CONFIG_NAME="efi_v8_defconfig"
 CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x0
 CONFIG_KALLSYMS=y
 CONFIG_PROMPT="barebox> "
 CONFIG_PROMPT_HUSH_PS2="y"
diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig
index cbdb3a65c745..c8dd3e227929 100644
--- a/arch/arm/configs/imx_v8_defconfig
+++ b/arch/arm/configs/imx_v8_defconfig
@@ -23,7 +23,6 @@ CONFIG_64BIT=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_NAME="imx_v8_defconfig"
 CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x0
 CONFIG_KALLSYMS=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_AUTO_COMPLETE=y
diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig
index 272dff90d7c8..7d2a2e2322a2 100644
--- a/arch/arm/configs/layerscape_defconfig
+++ b/arch/arm/configs/layerscape_defconfig
@@ -6,7 +6,6 @@ CONFIG_64BIT=y
 CONFIG_ARM_PSCI_CLIENT=y
 CONFIG_NAME="layerscape_defconfig"
 CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x0
 CONFIG_KALLSYMS=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig
index 233aebbe2d95..e62dbc96fd03 100644
--- a/arch/arm/configs/multi_v8_defconfig
+++ b/arch/arm/configs/multi_v8_defconfig
@@ -52,7 +52,6 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_PSCI_CLIENT=y
 CONFIG_NAME="multi_v8_defconfig"
 CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x0
 CONFIG_KALLSYMS=y
 CONFIG_PROMPT="barebox> "
 CONFIG_HUSH_FANCY_PROMPT=y
diff --git a/arch/arm/configs/rockchip_v8_defconfig b/arch/arm/configs/rockchip_v8_defconfig
index e0df655ea046..ef2951d133d6 100644
--- a/arch/arm/configs/rockchip_v8_defconfig
+++ b/arch/arm/configs/rockchip_v8_defconfig
@@ -16,7 +16,6 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_PSCI_CLIENT=y
 CONFIG_NAME="rockchip_v8_defconfig"
 CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
 CONFIG_PROMPT="barebox> "
diff --git a/arch/arm/configs/rpi_v8a_defconfig b/arch/arm/configs/rpi_v8a_defconfig
index 6c85209546e4..c29fe30701e8 100644
--- a/arch/arm/configs/rpi_v8a_defconfig
+++ b/arch/arm/configs/rpi_v8a_defconfig
@@ -6,7 +6,6 @@ CONFIG_64BIT=y
 CONFIG_IMAGE_COMPRESSION_NONE=y
 CONFIG_NAME="rpi_v8a_defconfig"
 CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
 CONFIG_PROMPT="R-Pi> "
@@ -111,4 +110,4 @@ CONFIG_FS_NFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_WRITE=y
 CONFIG_FS_FAT_LFN=y
-CONFIG_ZLIB=y
\ No newline at end of file
+CONFIG_ZLIB=y
diff --git a/arch/arm/configs/socfpga-agilex5_defconfig b/arch/arm/configs/socfpga-agilex5_defconfig
index 5711cb89ed27..cad8eeb862fe 100644
--- a/arch/arm/configs/socfpga-agilex5_defconfig
+++ b/arch/arm/configs/socfpga-agilex5_defconfig
@@ -3,7 +3,6 @@ CONFIG_64BIT=y
 CONFIG_MACH_SOCFPGA_ARROW_AXE5_EAGLE=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x0
 CONFIG_PROMPT="barebox> "
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
diff --git a/arch/arm/configs/zynqmp_defconfig b/arch/arm/configs/zynqmp_defconfig
index 5a71536ba69e..39c1b42619cc 100644
--- a/arch/arm/configs/zynqmp_defconfig
+++ b/arch/arm/configs/zynqmp_defconfig
@@ -6,7 +6,6 @@ CONFIG_64BIT=y
 CONFIG_ARM_PSCI_CLIENT=y
 CONFIG_NAME="zynqmp_defconfig"
 CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
 CONFIG_HUSH_FANCY_PROMPT=y
-- 
2.47.3

[PATCH master v2 5/5] ARM64: place PBL malloc area at start of barebox proper malloc area

[Ahmad Fatoum]

The early PBL malloc area used by the Rockchip code overlaps the region
used for OP-TEE. Moving it a bit lower would overlap the region occupied
by the scratch area.

With the switch to CONFIG_BAREBOX_MEMORY_OFFSET, we can compute the start
of the malloc area in barebox proper without knowing how big barebox will
eventually be, so make use of that and always place the PBL malloc area
exactly at the start of the eventual barebox proper memory area.

The memory will automatically be reclaimed when the TLSF allocator is
instantiated and we will be sure not to overwrite anything by allocating
in PBL.

Reported-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Fixes: 76b1f31275fe ("ARM: rockchip: initialize PBL malloc")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/cpu/common.c              |  5 +++++
 arch/arm/cpu/uncompress.c          |  4 ++++
 arch/arm/include/asm/barebox-arm.h | 10 ++++++----
 arch/arm/mach-rockchip/atf.c       |  2 +-
 4 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 6b82ee8b810c..adb5d6a02bc8 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -114,8 +114,13 @@ void print_pbl_mem_layout(ulong membase, ulong endmem, ulong barebox_base)
 #endif
 	printf("arm_mem_barebox_image = 0x%08lx+0x%08lx\n",
 	       barebox_base, arm_mem_barebox_image_end(endmem) - barebox_base);
+#ifdef CONFIG_ARM64
+	printf("pbl_malloc area       = 0x%08lx+0x%08x\n",
+	       barebox_malloc_base(membase, endmem - membase), PBL_MALLOC_SIZE);
+#else
 	printf("arm_mem_early_malloc  = 0x%08lx+0x%08x\n",
 	       barebox_base - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
+#endif
 	printf("membase               = 0x%08lx+0x%08lx\n",
 	       membase, endmem - membase);
 }
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 61bcba6e8549..55bbe0019cc4 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -75,7 +75,11 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
 
 	handoff_data = (void *)barebox_base + ALIGN(uncompressed_len, 8) + MAX_BSS_SIZE;
 
+#ifdef CONFIG_ARM64
+	pbl_malloc_init(barebox_malloc_base(membase, memsize), PBL_MALLOC_SIZE);
+#else
 	pbl_malloc_init(barebox_base - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
+#endif
 
 #ifdef DEBUG
 	print_pbl_mem_layout(membase, endmem, barebox_base);
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 38cceba010ed..f75cddc77243 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -95,10 +95,12 @@ void *barebox_arm_boot_dtb(void);
  *                       + BSS) rounded to SZ_1M
  *                                   ↓
  *  ---------------------- arm_mem_barebox_image() ---------------------
- *                                   ↑
- *                                SZ_128K
- *                                   ↓
- *  ------------------------ arm_mem_early_malloc ----------------------
+ *     ARM32      ↑                  |                ↕         ARM64
+ *         PBL_MALLOC_SIZE           |------- pbl_malloc area end ------
+ *                ↓                  |                ↑
+ *  --- arm_mem_early_malloc --------|         PBL_MALLOC_SIZE
+ *                                   |                ↓
+ *                                   ----- pbl_malloc area start -------
  */
 void print_pbl_mem_layout(ulong membase, ulong endmem, ulong barebox_base);
 
diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
index 14797a1e0601..f9dbc8b20c5a 100644
--- a/arch/arm/mach-rockchip/atf.c
+++ b/arch/arm/mach-rockchip/atf.c
@@ -173,7 +173,7 @@ static void rockchip_atf_load_bl31(void *fdt)
 	unsigned long bl31_ep;
 
 	mmu_early_enable(membase[0], memsize[0]);
-	pbl_malloc_init(membase[0] + memsize[0] - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
+	pbl_malloc_init(membase[0], memsize[0]);
 
 	bl31_ep = load_elf64_image_phdr(&bl31);
 
-- 
2.47.3

Re: [PATCH master v2 5/5] ARM64: place PBL malloc area at start of barebox proper malloc area

[Alexander Shiyan]

Tested-by: Alexander Shiyan <eagle.alexander923@gmail.com>

ср, 27 мая 2026 г. в 15:17, Ahmad Fatoum <a.fatoum@pengutronix.de>:
>
> The early PBL malloc area used by the Rockchip code overlaps the region
> used for OP-TEE. Moving it a bit lower would overlap the region occupied
> by the scratch area.
>
> With the switch to CONFIG_BAREBOX_MEMORY_OFFSET, we can compute the start
> of the malloc area in barebox proper without knowing how big barebox will
> eventually be, so make use of that and always place the PBL malloc area
> exactly at the start of the eventual barebox proper memory area.
>
> The memory will automatically be reclaimed when the TLSF allocator is
> instantiated and we will be sure not to overwrite anything by allocating
> in PBL.
>
> Reported-by: Alexander Shiyan <eagle.alexander923@gmail.com>
> Fixes: 76b1f31275fe ("ARM: rockchip: initialize PBL malloc")
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  arch/arm/cpu/common.c              |  5 +++++
>  arch/arm/cpu/uncompress.c          |  4 ++++
>  arch/arm/include/asm/barebox-arm.h | 10 ++++++----
>  arch/arm/mach-rockchip/atf.c       |  2 +-
>  4 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
> index 6b82ee8b810c..adb5d6a02bc8 100644
> --- a/arch/arm/cpu/common.c
> +++ b/arch/arm/cpu/common.c
> @@ -114,8 +114,13 @@ void print_pbl_mem_layout(ulong membase, ulong endmem, ulong barebox_base)
>  #endif
>         printf("arm_mem_barebox_image = 0x%08lx+0x%08lx\n",
>                barebox_base, arm_mem_barebox_image_end(endmem) - barebox_base);
> +#ifdef CONFIG_ARM64
> +       printf("pbl_malloc area       = 0x%08lx+0x%08x\n",
> +              barebox_malloc_base(membase, endmem - membase), PBL_MALLOC_SIZE);
> +#else
>         printf("arm_mem_early_malloc  = 0x%08lx+0x%08x\n",
>                barebox_base - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
> +#endif
>         printf("membase               = 0x%08lx+0x%08lx\n",
>                membase, endmem - membase);
>  }
> diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
> index 61bcba6e8549..55bbe0019cc4 100644
> --- a/arch/arm/cpu/uncompress.c
> +++ b/arch/arm/cpu/uncompress.c
> @@ -75,7 +75,11 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
>
>         handoff_data = (void *)barebox_base + ALIGN(uncompressed_len, 8) + MAX_BSS_SIZE;
>
> +#ifdef CONFIG_ARM64
> +       pbl_malloc_init(barebox_malloc_base(membase, memsize), PBL_MALLOC_SIZE);
> +#else
>         pbl_malloc_init(barebox_base - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
> +#endif
>
>  #ifdef DEBUG
>         print_pbl_mem_layout(membase, endmem, barebox_base);
> diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
> index 38cceba010ed..f75cddc77243 100644
> --- a/arch/arm/include/asm/barebox-arm.h
> +++ b/arch/arm/include/asm/barebox-arm.h
> @@ -95,10 +95,12 @@ void *barebox_arm_boot_dtb(void);
>   *                       + BSS) rounded to SZ_1M
>   *                                   ↓
>   *  ---------------------- arm_mem_barebox_image() ---------------------
> - *                                   ↑
> - *                                SZ_128K
> - *                                   ↓
> - *  ------------------------ arm_mem_early_malloc ----------------------
> + *     ARM32      ↑                  |                ↕         ARM64
> + *         PBL_MALLOC_SIZE           |------- pbl_malloc area end ------
> + *                ↓                  |                ↑
> + *  --- arm_mem_early_malloc --------|         PBL_MALLOC_SIZE
> + *                                   |                ↓
> + *                                   ----- pbl_malloc area start -------
>   */
>  void print_pbl_mem_layout(ulong membase, ulong endmem, ulong barebox_base);
>
> diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
> index 14797a1e0601..f9dbc8b20c5a 100644
> --- a/arch/arm/mach-rockchip/atf.c
> +++ b/arch/arm/mach-rockchip/atf.c
> @@ -173,7 +173,7 @@ static void rockchip_atf_load_bl31(void *fdt)
>         unsigned long bl31_ep;
>
>         mmu_early_enable(membase[0], memsize[0]);
> -       pbl_malloc_init(membase[0] + memsize[0] - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
> +       pbl_malloc_init(membase[0], memsize[0]);
>
>         bl31_ep = load_elf64_image_phdr(&bl31);
>
> --
> 2.47.3
>

[PATCH master v2] fixup! ARM64: place PBL malloc area at start of barebox proper malloc area

[Ahmad Fatoum]

ARM64: rockchip: atf: place PBL malloc area within barebox proper malloc area

We should restrict pbl_malloc_init to PBL_MALLOC_SIZE as memsize[0] as a
whole also contains non-malloc area parts like barebox proper location,
the stack and the OP-TEE region if any.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-rockchip/atf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
index f9dbc8b20c5a..8e10d6af445d 100644
--- a/arch/arm/mach-rockchip/atf.c
+++ b/arch/arm/mach-rockchip/atf.c
@@ -173,7 +173,7 @@ static void rockchip_atf_load_bl31(void *fdt)
 	unsigned long bl31_ep;
 
 	mmu_early_enable(membase[0], memsize[0]);
-	pbl_malloc_init(membase[0], memsize[0]);
+	pbl_malloc_init(membase[0], PBL_MALLOC_SIZE);
 
 	bl31_ep = load_elf64_image_phdr(&bl31);
 
-- 
2.47.3

Re: [PATCH master v2 5/5] ARM64: place PBL malloc area at start of barebox proper malloc area

[Ahmad Fatoum]

Hi,

On 5/27/26 3:12 PM, Alexander Shiyan wrote:
> Tested-by: Alexander Shiyan <eagle.alexander923@gmail.com>

Unfortunately, I placed the very early malloc area at the wrong place.

I just sent out v3 and would appreciate if you can check if that also
works for you.

Cheers,
Ahmad

> 
> ср, 27 мая 2026 г. в 15:17, Ahmad Fatoum <a.fatoum@pengutronix.de>:
>>
>> The early PBL malloc area used by the Rockchip code overlaps the region
>> used for OP-TEE. Moving it a bit lower would overlap the region occupied
>> by the scratch area.
>>
>> With the switch to CONFIG_BAREBOX_MEMORY_OFFSET, we can compute the start
>> of the malloc area in barebox proper without knowing how big barebox will
>> eventually be, so make use of that and always place the PBL malloc area
>> exactly at the start of the eventual barebox proper memory area.
>>
>> The memory will automatically be reclaimed when the TLSF allocator is
>> instantiated and we will be sure not to overwrite anything by allocating
>> in PBL.
>>
>> Reported-by: Alexander Shiyan <eagle.alexander923@gmail.com>
>> Fixes: 76b1f31275fe ("ARM: rockchip: initialize PBL malloc")
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---
>>  arch/arm/cpu/common.c              |  5 +++++
>>  arch/arm/cpu/uncompress.c          |  4 ++++
>>  arch/arm/include/asm/barebox-arm.h | 10 ++++++----
>>  arch/arm/mach-rockchip/atf.c       |  2 +-
>>  4 files changed, 16 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
>> index 6b82ee8b810c..adb5d6a02bc8 100644
>> --- a/arch/arm/cpu/common.c
>> +++ b/arch/arm/cpu/common.c
>> @@ -114,8 +114,13 @@ void print_pbl_mem_layout(ulong membase, ulong endmem, ulong barebox_base)
>>  #endif
>>         printf("arm_mem_barebox_image = 0x%08lx+0x%08lx\n",
>>                barebox_base, arm_mem_barebox_image_end(endmem) - barebox_base);
>> +#ifdef CONFIG_ARM64
>> +       printf("pbl_malloc area       = 0x%08lx+0x%08x\n",
>> +              barebox_malloc_base(membase, endmem - membase), PBL_MALLOC_SIZE);
>> +#else
>>         printf("arm_mem_early_malloc  = 0x%08lx+0x%08x\n",
>>                barebox_base - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
>> +#endif
>>         printf("membase               = 0x%08lx+0x%08lx\n",
>>                membase, endmem - membase);
>>  }
>> diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
>> index 61bcba6e8549..55bbe0019cc4 100644
>> --- a/arch/arm/cpu/uncompress.c
>> +++ b/arch/arm/cpu/uncompress.c
>> @@ -75,7 +75,11 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
>>
>>         handoff_data = (void *)barebox_base + ALIGN(uncompressed_len, 8) + MAX_BSS_SIZE;
>>
>> +#ifdef CONFIG_ARM64
>> +       pbl_malloc_init(barebox_malloc_base(membase, memsize), PBL_MALLOC_SIZE);
>> +#else
>>         pbl_malloc_init(barebox_base - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
>> +#endif
>>
>>  #ifdef DEBUG
>>         print_pbl_mem_layout(membase, endmem, barebox_base);
>> diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
>> index 38cceba010ed..f75cddc77243 100644
>> --- a/arch/arm/include/asm/barebox-arm.h
>> +++ b/arch/arm/include/asm/barebox-arm.h
>> @@ -95,10 +95,12 @@ void *barebox_arm_boot_dtb(void);
>>   *                       + BSS) rounded to SZ_1M
>>   *                                   ↓
>>   *  ---------------------- arm_mem_barebox_image() ---------------------
>> - *                                   ↑
>> - *                                SZ_128K
>> - *                                   ↓
>> - *  ------------------------ arm_mem_early_malloc ----------------------
>> + *     ARM32      ↑                  |                ↕         ARM64
>> + *         PBL_MALLOC_SIZE           |------- pbl_malloc area end ------
>> + *                ↓                  |                ↑
>> + *  --- arm_mem_early_malloc --------|         PBL_MALLOC_SIZE
>> + *                                   |                ↓
>> + *                                   ----- pbl_malloc area start -------
>>   */
>>  void print_pbl_mem_layout(ulong membase, ulong endmem, ulong barebox_base);
>>
>> diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
>> index 14797a1e0601..f9dbc8b20c5a 100644
>> --- a/arch/arm/mach-rockchip/atf.c
>> +++ b/arch/arm/mach-rockchip/atf.c
>> @@ -173,7 +173,7 @@ static void rockchip_atf_load_bl31(void *fdt)
>>         unsigned long bl31_ep;
>>
>>         mmu_early_enable(membase[0], memsize[0]);
>> -       pbl_malloc_init(membase[0] + memsize[0] - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
>> +       pbl_malloc_init(membase[0], memsize[0]);
>>
>>         bl31_ep = load_elf64_image_phdr(&bl31);
>>
>> --
>> 2.47.3
>>
> 

-- 
Pengutronix e.K.                  |                             |
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31137 Hildesheim, Germany         | Phone: +49-5121-206917-0    |
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Re: [PATCH master v2 0/5] ARM64: unify pbl and proper malloc area start

[Sascha Hauer]

On Wed, 27 May 2026 14:15:19 +0200, Ahmad Fatoum wrote:
> The current location used to place the very early PBL malloc area on
> Rockchip overlaps the OP-TEE region. This series changes ARM64 to
> make the start of the barebox proper malloc area easier to calculate and
> uses that also for the PBL memory region.
> 
> v1: https://lore.barebox.org/barebox/20260522105852.2681680-1-a.fatoum@pengutronix.de/
> 
> [...]

Applied, thanks!

[1/5] arch: introduce new CONFIG_ARCH_HAS_MALLOC_SIZE
      https://git.pengutronix.de/cgit/barebox/commit/?id=660163f709e3 (link may not be stable)
[2/5] arch: introduce CONFIG_BAREBOX_MEMORY_OFFSET
      https://git.pengutronix.de/cgit/barebox/commit/?id=2f63ce43a399 (link may not be stable)
[3/5] ARM64: switch to CONFIG_BAREBOX_MEMORY_OFFSET
      https://git.pengutronix.de/cgit/barebox/commit/?id=a4e8173a985e (link may not be stable)
[4/5] ARM64: configs: drop CONFIG_MALLOC_SIZE=0x0 as it's now the default
      https://git.pengutronix.de/cgit/barebox/commit/?id=f2a6431a7a38 (link may not be stable)
[5/5] ARM64: place PBL malloc area at start of barebox proper malloc area
      https://git.pengutronix.de/cgit/barebox/commit/?id=81fbe2e8d0d4 (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>

Re: [PATCH master v2] fixup! ARM64: place PBL malloc area at start of barebox proper malloc area

[Alexander Shiyan]

Tested-by: Alexander Shiyan <eagle.alexander923@gmail.com>

чт, 28 мая 2026 г. в 14:20, Ahmad Fatoum <a.fatoum@pengutronix.de>:
>
> ARM64: rockchip: atf: place PBL malloc area within barebox proper malloc area
>
> We should restrict pbl_malloc_init to PBL_MALLOC_SIZE as memsize[0] as a
> whole also contains non-malloc area parts like barebox proper location,
> the stack and the OP-TEE region if any.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  arch/arm/mach-rockchip/atf.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
> index f9dbc8b20c5a..8e10d6af445d 100644
> --- a/arch/arm/mach-rockchip/atf.c
> +++ b/arch/arm/mach-rockchip/atf.c
> @@ -173,7 +173,7 @@ static void rockchip_atf_load_bl31(void *fdt)
>         unsigned long bl31_ep;
>
>         mmu_early_enable(membase[0], memsize[0]);
> -       pbl_malloc_init(membase[0], memsize[0]);
> +       pbl_malloc_init(membase[0], PBL_MALLOC_SIZE);
>
>         bl31_ep = load_elf64_image_phdr(&bl31);
>
> --
> 2.47.3
>
>

Re: [PATCH master v2 5/5] ARM64: place PBL malloc area at start of barebox proper malloc area

[Alexander Shiyan]

Hello Ahmad.

Just checked the fixup.

чт, 28 мая 2026 г. в 14:04, Ahmad Fatoum <a.fatoum@pengutronix.de>:
>
> Hi,
>
> On 5/27/26 3:12 PM, Alexander Shiyan wrote:
> > Tested-by: Alexander Shiyan <eagle.alexander923@gmail.com>
>
> Unfortunately, I placed the very early malloc area at the wrong place.
>
> I just sent out v3 and would appreciate if you can check if that also
> works for you.
>
> Cheers,
> Ahmad
>
> >
> > ср, 27 мая 2026 г. в 15:17, Ahmad Fatoum <a.fatoum@pengutronix.de>:
> >>
> >> The early PBL malloc area used by the Rockchip code overlaps the region
> >> used for OP-TEE. Moving it a bit lower would overlap the region occupied
> >> by the scratch area.
> >>
> >> With the switch to CONFIG_BAREBOX_MEMORY_OFFSET, we can compute the start
> >> of the malloc area in barebox proper without knowing how big barebox will
> >> eventually be, so make use of that and always place the PBL malloc area
> >> exactly at the start of the eventual barebox proper memory area.
> >>
> >> The memory will automatically be reclaimed when the TLSF allocator is
> >> instantiated and we will be sure not to overwrite anything by allocating
> >> in PBL.
> >>
> >> Reported-by: Alexander Shiyan <eagle.alexander923@gmail.com>
> >> Fixes: 76b1f31275fe ("ARM: rockchip: initialize PBL malloc")
> >> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> >> ---
> >>  arch/arm/cpu/common.c              |  5 +++++
> >>  arch/arm/cpu/uncompress.c          |  4 ++++
> >>  arch/arm/include/asm/barebox-arm.h | 10 ++++++----
> >>  arch/arm/mach-rockchip/atf.c       |  2 +-
> >>  4 files changed, 16 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
> >> index 6b82ee8b810c..adb5d6a02bc8 100644
> >> --- a/arch/arm/cpu/common.c
> >> +++ b/arch/arm/cpu/common.c
> >> @@ -114,8 +114,13 @@ void print_pbl_mem_layout(ulong membase, ulong endmem, ulong barebox_base)
> >>  #endif
> >>         printf("arm_mem_barebox_image = 0x%08lx+0x%08lx\n",
> >>                barebox_base, arm_mem_barebox_image_end(endmem) - barebox_base);
> >> +#ifdef CONFIG_ARM64
> >> +       printf("pbl_malloc area       = 0x%08lx+0x%08x\n",
> >> +              barebox_malloc_base(membase, endmem - membase), PBL_MALLOC_SIZE);
> >> +#else
> >>         printf("arm_mem_early_malloc  = 0x%08lx+0x%08x\n",
> >>                barebox_base - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
> >> +#endif
> >>         printf("membase               = 0x%08lx+0x%08lx\n",
> >>                membase, endmem - membase);
> >>  }
> >> diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
> >> index 61bcba6e8549..55bbe0019cc4 100644
> >> --- a/arch/arm/cpu/uncompress.c
> >> +++ b/arch/arm/cpu/uncompress.c
> >> @@ -75,7 +75,11 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
> >>
> >>         handoff_data = (void *)barebox_base + ALIGN(uncompressed_len, 8) + MAX_BSS_SIZE;
> >>
> >> +#ifdef CONFIG_ARM64
> >> +       pbl_malloc_init(barebox_malloc_base(membase, memsize), PBL_MALLOC_SIZE);
> >> +#else
> >>         pbl_malloc_init(barebox_base - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
> >> +#endif
> >>
> >>  #ifdef DEBUG
> >>         print_pbl_mem_layout(membase, endmem, barebox_base);
> >> diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
> >> index 38cceba010ed..f75cddc77243 100644
> >> --- a/arch/arm/include/asm/barebox-arm.h
> >> +++ b/arch/arm/include/asm/barebox-arm.h
> >> @@ -95,10 +95,12 @@ void *barebox_arm_boot_dtb(void);
> >>   *                       + BSS) rounded to SZ_1M
> >>   *                                   ↓
> >>   *  ---------------------- arm_mem_barebox_image() ---------------------
> >> - *                                   ↑
> >> - *                                SZ_128K
> >> - *                                   ↓
> >> - *  ------------------------ arm_mem_early_malloc ----------------------
> >> + *     ARM32      ↑                  |                ↕         ARM64
> >> + *         PBL_MALLOC_SIZE           |------- pbl_malloc area end ------
> >> + *                ↓                  |                ↑
> >> + *  --- arm_mem_early_malloc --------|         PBL_MALLOC_SIZE
> >> + *                                   |                ↓
> >> + *                                   ----- pbl_malloc area start -------
> >>   */
> >>  void print_pbl_mem_layout(ulong membase, ulong endmem, ulong barebox_base);
> >>
> >> diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
> >> index 14797a1e0601..f9dbc8b20c5a 100644
> >> --- a/arch/arm/mach-rockchip/atf.c
> >> +++ b/arch/arm/mach-rockchip/atf.c
> >> @@ -173,7 +173,7 @@ static void rockchip_atf_load_bl31(void *fdt)
> >>         unsigned long bl31_ep;
> >>
> >>         mmu_early_enable(membase[0], memsize[0]);
> >> -       pbl_malloc_init(membase[0] + memsize[0] - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
> >> +       pbl_malloc_init(membase[0], memsize[0]);
> >>
> >>         bl31_ep = load_elf64_image_phdr(&bl31);
> >>
> >> --
> >> 2.47.3
> >>
> >
>
> --
> Pengutronix e.K.                  |                             |
> Steuerwalder Str. 21              | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany         | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686  | Fax:   +49-5121-206917-5555 |
>

Re: [PATCH master v2 5/5] ARM64: place PBL malloc area at start of barebox proper malloc area

[Ahmad Fatoum]

Hello Alexander,

On 5/28/26 2:17 PM, Alexander Shiyan wrote:
> Hello Ahmad.
> 
> Just checked the fixup.

I had botched the fixup, right in the place that's relevant to your
regression. :(

v3 has the correct location now.

Sorry for the noise.
Ahmad

> 
> чт, 28 мая 2026 г. в 14:04, Ahmad Fatoum <a.fatoum@pengutronix.de>:
>>
>> Hi,
>>
>> On 5/27/26 3:12 PM, Alexander Shiyan wrote:
>>> Tested-by: Alexander Shiyan <eagle.alexander923@gmail.com>
>>
>> Unfortunately, I placed the very early malloc area at the wrong place.
>>
>> I just sent out v3 and would appreciate if you can check if that also
>> works for you.
>>
>> Cheers,
>> Ahmad
>>
>>>
>>> ср, 27 мая 2026 г. в 15:17, Ahmad Fatoum <a.fatoum@pengutronix.de>:
>>>>
>>>> The early PBL malloc area used by the Rockchip code overlaps the region
>>>> used for OP-TEE. Moving it a bit lower would overlap the region occupied
>>>> by the scratch area.
>>>>
>>>> With the switch to CONFIG_BAREBOX_MEMORY_OFFSET, we can compute the start
>>>> of the malloc area in barebox proper without knowing how big barebox will
>>>> eventually be, so make use of that and always place the PBL malloc area
>>>> exactly at the start of the eventual barebox proper memory area.
>>>>
>>>> The memory will automatically be reclaimed when the TLSF allocator is
>>>> instantiated and we will be sure not to overwrite anything by allocating
>>>> in PBL.
>>>>
>>>> Reported-by: Alexander Shiyan <eagle.alexander923@gmail.com>
>>>> Fixes: 76b1f31275fe ("ARM: rockchip: initialize PBL malloc")
>>>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>>>> ---
>>>>  arch/arm/cpu/common.c              |  5 +++++
>>>>  arch/arm/cpu/uncompress.c          |  4 ++++
>>>>  arch/arm/include/asm/barebox-arm.h | 10 ++++++----
>>>>  arch/arm/mach-rockchip/atf.c       |  2 +-
>>>>  4 files changed, 16 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
>>>> index 6b82ee8b810c..adb5d6a02bc8 100644
>>>> --- a/arch/arm/cpu/common.c
>>>> +++ b/arch/arm/cpu/common.c
>>>> @@ -114,8 +114,13 @@ void print_pbl_mem_layout(ulong membase, ulong endmem, ulong barebox_base)
>>>>  #endif
>>>>         printf("arm_mem_barebox_image = 0x%08lx+0x%08lx\n",
>>>>                barebox_base, arm_mem_barebox_image_end(endmem) - barebox_base);
>>>> +#ifdef CONFIG_ARM64
>>>> +       printf("pbl_malloc area       = 0x%08lx+0x%08x\n",
>>>> +              barebox_malloc_base(membase, endmem - membase), PBL_MALLOC_SIZE);
>>>> +#else
>>>>         printf("arm_mem_early_malloc  = 0x%08lx+0x%08x\n",
>>>>                barebox_base - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
>>>> +#endif
>>>>         printf("membase               = 0x%08lx+0x%08lx\n",
>>>>                membase, endmem - membase);
>>>>  }
>>>> diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
>>>> index 61bcba6e8549..55bbe0019cc4 100644
>>>> --- a/arch/arm/cpu/uncompress.c
>>>> +++ b/arch/arm/cpu/uncompress.c
>>>> @@ -75,7 +75,11 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
>>>>
>>>>         handoff_data = (void *)barebox_base + ALIGN(uncompressed_len, 8) + MAX_BSS_SIZE;
>>>>
>>>> +#ifdef CONFIG_ARM64
>>>> +       pbl_malloc_init(barebox_malloc_base(membase, memsize), PBL_MALLOC_SIZE);
>>>> +#else
>>>>         pbl_malloc_init(barebox_base - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
>>>> +#endif
>>>>
>>>>  #ifdef DEBUG
>>>>         print_pbl_mem_layout(membase, endmem, barebox_base);
>>>> diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
>>>> index 38cceba010ed..f75cddc77243 100644
>>>> --- a/arch/arm/include/asm/barebox-arm.h
>>>> +++ b/arch/arm/include/asm/barebox-arm.h
>>>> @@ -95,10 +95,12 @@ void *barebox_arm_boot_dtb(void);
>>>>   *                       + BSS) rounded to SZ_1M
>>>>   *                                   ↓
>>>>   *  ---------------------- arm_mem_barebox_image() ---------------------
>>>> - *                                   ↑
>>>> - *                                SZ_128K
>>>> - *                                   ↓
>>>> - *  ------------------------ arm_mem_early_malloc ----------------------
>>>> + *     ARM32      ↑                  |                ↕         ARM64
>>>> + *         PBL_MALLOC_SIZE           |------- pbl_malloc area end ------
>>>> + *                ↓                  |                ↑
>>>> + *  --- arm_mem_early_malloc --------|         PBL_MALLOC_SIZE
>>>> + *                                   |                ↓
>>>> + *                                   ----- pbl_malloc area start -------
>>>>   */
>>>>  void print_pbl_mem_layout(ulong membase, ulong endmem, ulong barebox_base);
>>>>
>>>> diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
>>>> index 14797a1e0601..f9dbc8b20c5a 100644
>>>> --- a/arch/arm/mach-rockchip/atf.c
>>>> +++ b/arch/arm/mach-rockchip/atf.c
>>>> @@ -173,7 +173,7 @@ static void rockchip_atf_load_bl31(void *fdt)
>>>>         unsigned long bl31_ep;
>>>>
>>>>         mmu_early_enable(membase[0], memsize[0]);
>>>> -       pbl_malloc_init(membase[0] + memsize[0] - PBL_MALLOC_SIZE, PBL_MALLOC_SIZE);
>>>> +       pbl_malloc_init(membase[0], memsize[0]);
>>>>
>>>>         bl31_ep = load_elf64_image_phdr(&bl31);
>>>>
>>>> --
>>>> 2.47.3
>>>>
>>>
>>
>> --
>> Pengutronix e.K.                  |                             |
>> Steuerwalder Str. 21              | http://www.pengutronix.de/  |
>> 31137 Hildesheim, Germany         | Phone: +49-5121-206917-0    |
>> Amtsgericht Hildesheim, HRA 2686  | Fax:   +49-5121-206917-5555 |
>>
> 

-- 
Pengutronix e.K.                  |                             |
Steuerwalder Str. 21              | http://www.pengutronix.de/  |
31137 Hildesheim, Germany         | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686  | Fax:   +49-5121-206917-5555 |