From: "Barbier, Renaud" <renaud.barbier@abaco.com>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>,
"barebox@lists.infradead.org" <barebox@lists.infradead.org>
Subject: RE: Uart set up in PBL
Date: Fri, 5 Mar 2021 13:08:16 +0000 [thread overview]
Message-ID: <MN2PR16MB3135E6DF1FAD29294046059391969@MN2PR16MB3135.namprd16.prod.outlook.com> (raw)
In-Reply-To: <c3eae1a0-2296-64f4-95ea-cb808f1f0aa2@pengutronix.de>
>
> So you load pbl/bare init barebox into SRAM, run PBIT memory test on DRAM,
> then extract/copy barebox proper to DRAM or how does it work?
>
[Barbier, Renaud]
For now I have never used PBL on ARM (lwl-y => obj-y). Probably did not do right as I tweaked the barebox linker script to have a TEXT_BASE. Only reason I did not use PBL is that it did not boot first few time I tried and the other way worked right away.
PBIT runs from SPI NOR flash which is not a problem as there is a DDR BIST unit on our ARM SOC. I did include the memtester from pyropus.ca too for a more comprehensive test and obviously it is very slow running from flash with D-cache off. An improvement would be to run from SRAM.
>From the barebox_arm-reset_vector, the uart is set to a fixed baud rate, the DDR memory initialized and if PBIT is enabled a quick or comprehensive test is ran. Otherwise use the BIST to initialise ECC if present and then barebox_arm_entry is called to relocate barebox in memory.
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next prev parent reply other threads:[~2021-03-05 13:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-04 12:28 Barbier, Renaud
2021-03-04 12:59 ` Ahmad Fatoum
2021-03-04 16:41 ` Barbier, Renaud
2021-03-05 10:48 ` Ahmad Fatoum
2021-03-05 13:08 ` Barbier, Renaud [this message]
2021-03-08 20:22 ` Ahmad Fatoum
2021-03-04 13:07 ` Sascha Hauer
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