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* [PATCH master] RISC-V: cpu: fix build with CONFIG_RISCV_EXCEPTIONS=n
@ 2021-12-04 13:08 Ahmad Fatoum
  2021-12-07  9:06 ` Sascha Hauer
  0 siblings, 1 reply; 3+ messages in thread
From: Ahmad Fatoum @ 2021-12-04 13:08 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum, Yann Sionneau

Building without CONFIG_RISCV_EXCEPTIONS causes a compile error, because
of a definition mismatch. data_abort_mask is a no-op without exception
support, but interrupt.c defines it as a different type of symbol. Skip
interrupt.c compilation to fix the build error.

Reported-by: Yann Sionneau <ysionneau@kalray.eu>
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
 arch/riscv/cpu/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
index 717baaaaa727..d79bafc6f142 100644
--- a/arch/riscv/cpu/Makefile
+++ b/arch/riscv/cpu/Makefile
@@ -2,6 +2,8 @@
 
 obj-y += core.o time.o
 obj-$(CONFIG_HAS_DMA) += dma.o
+ifeq ($(CONFIG_RISCV_EXCEPTIONS),y)
 obj-pbl-$(CONFIG_RISCV_M_MODE) += mtrap.o
 obj-pbl-$(CONFIG_RISCV_S_MODE) += strap.o
 obj-pbl-y += interrupts.o
+endif
-- 
2.33.0


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^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH master] RISC-V: cpu: fix build with CONFIG_RISCV_EXCEPTIONS=n
  2021-12-04 13:08 [PATCH master] RISC-V: cpu: fix build with CONFIG_RISCV_EXCEPTIONS=n Ahmad Fatoum
@ 2021-12-07  9:06 ` Sascha Hauer
  2022-01-03 10:25   ` Ahmad Fatoum
  0 siblings, 1 reply; 3+ messages in thread
From: Sascha Hauer @ 2021-12-07  9:06 UTC (permalink / raw)
  To: Ahmad Fatoum; +Cc: barebox, Yann Sionneau

On Sat, Dec 04, 2021 at 02:08:54PM +0100, Ahmad Fatoum wrote:
> Building without CONFIG_RISCV_EXCEPTIONS causes a compile error, because
> of a definition mismatch. data_abort_mask is a no-op without exception
> support, but interrupt.c defines it as a different type of symbol. Skip
> interrupt.c compilation to fix the build error.
> 
> Reported-by: Yann Sionneau <ysionneau@kalray.eu>
> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
> ---
>  arch/riscv/cpu/Makefile | 2 ++
>  1 file changed, 2 insertions(+)

Applied, thanks

Sascha

> 
> diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
> index 717baaaaa727..d79bafc6f142 100644
> --- a/arch/riscv/cpu/Makefile
> +++ b/arch/riscv/cpu/Makefile
> @@ -2,6 +2,8 @@
>  
>  obj-y += core.o time.o
>  obj-$(CONFIG_HAS_DMA) += dma.o
> +ifeq ($(CONFIG_RISCV_EXCEPTIONS),y)
>  obj-pbl-$(CONFIG_RISCV_M_MODE) += mtrap.o
>  obj-pbl-$(CONFIG_RISCV_S_MODE) += strap.o
>  obj-pbl-y += interrupts.o
> +endif
> -- 
> 2.33.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH master] RISC-V: cpu: fix build with CONFIG_RISCV_EXCEPTIONS=n
  2021-12-07  9:06 ` Sascha Hauer
@ 2022-01-03 10:25   ` Ahmad Fatoum
  0 siblings, 0 replies; 3+ messages in thread
From: Ahmad Fatoum @ 2022-01-03 10:25 UTC (permalink / raw)
  To: Sascha Hauer, Ahmad Fatoum; +Cc: barebox, Yann Sionneau

Hello Sascha,

On 07.12.21 10:06, Sascha Hauer wrote:
> On Sat, Dec 04, 2021 at 02:08:54PM +0100, Ahmad Fatoum wrote:
>> Building without CONFIG_RISCV_EXCEPTIONS causes a compile error, because
>> of a definition mismatch. data_abort_mask is a no-op without exception
>> support, but interrupt.c defines it as a different type of symbol. Skip
>> interrupt.c compilation to fix the build error.

I don't find this patch in either master or next.
Can you push it?

Thanks,
Ahmad

>>
>> Reported-by: Yann Sionneau <ysionneau@kalray.eu>
>> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
>> ---
>>  arch/riscv/cpu/Makefile | 2 ++
>>  1 file changed, 2 insertions(+)
> 
> Applied, thanks
> 
> Sascha
> 
>>
>> diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
>> index 717baaaaa727..d79bafc6f142 100644
>> --- a/arch/riscv/cpu/Makefile
>> +++ b/arch/riscv/cpu/Makefile
>> @@ -2,6 +2,8 @@
>>  
>>  obj-y += core.o time.o
>>  obj-$(CONFIG_HAS_DMA) += dma.o
>> +ifeq ($(CONFIG_RISCV_EXCEPTIONS),y)
>>  obj-pbl-$(CONFIG_RISCV_M_MODE) += mtrap.o
>>  obj-pbl-$(CONFIG_RISCV_S_MODE) += strap.o
>>  obj-pbl-y += interrupts.o
>> +endif
>> -- 
>> 2.33.0
>>
>>
>> _______________________________________________
>> barebox mailing list
>> barebox@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/barebox
>>
> 


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-01-03 10:27 UTC | newest]

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2021-12-04 13:08 [PATCH master] RISC-V: cpu: fix build with CONFIG_RISCV_EXCEPTIONS=n Ahmad Fatoum
2021-12-07  9:06 ` Sascha Hauer
2022-01-03 10:25   ` Ahmad Fatoum

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