[PATCH 0/6] arm: socfpga: agilex5: cleanup QSPI flash low level code

[PATCH 0/6] arm: socfpga: agilex5: cleanup QSPI flash low level code

[Michael Tretter]

On Agilex 5, barebox runs in the HPS (hard processor system) which needs
to explicitly request QSPI flash access from the SDM (secure device
manager). This request may be denied by the SDM. Furthermore, barebox
needs to store the clock rate reported by the SDM.

Cleanup and refactor the code that handles the QSPI flash request from
the SDM. This is a preparation for eventually reading a second stage
boot loader from QSPI flash.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
Michael Tretter (6):
      arm: socfpga: agilex5: add missing include soc64-regs.h
      arm: socfgpa: agilex5: remove mailbox_s10 from barebox proper
      arm: socfpga: agilex5: extract function to request qspi access
      arm: socfpga: mailbox_s10: keep clock rate in Hz
      arm: socfpga: mailbox_s10: add write_qspi_refclk helper
      arm: socfpga: agilex5: extract write_qspi_refclk from mailbox

 arch/arm/mach-socfpga/Makefile              |  1 -
 arch/arm/mach-socfpga/atf.c                 | 27 +++++++++++++++++++++++++--
 arch/arm/mach-socfpga/mailbox_s10.c         | 23 ++++++++---------------
 include/mach/socfpga/mailbox_s10.h          |  2 +-
 include/mach/socfpga/soc64-firewall.h       |  2 ++
 include/mach/socfpga/soc64-system-manager.h | 21 +++++++++++++++++++++
 6 files changed, 57 insertions(+), 19 deletions(-)
---
base-commit: 7a178f01f6e25474a5eb6e071ca479076b8d4d92
change-id: 20260505-socfpga-agilex5-qspi-5cb9abd175a8

Best regards,
-- 
Michael Tretter <m.tretter@pengutronix.de>

[PATCH 1/6] arm: socfpga: agilex5: add missing include soc64-regs.h

[Michael Tretter]

soc64-firewall.h defines macros that use register values that are
defined in soc64-regs.h. Include the appropriate header to make sure
that the definitions are available and users don't have to include the
headers in the correct order.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 include/mach/socfpga/soc64-firewall.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/mach/socfpga/soc64-firewall.h b/include/mach/socfpga/soc64-firewall.h
index 659b84ca1f3f..0187e908594c 100644
--- a/include/mach/socfpga/soc64-firewall.h
+++ b/include/mach/socfpga/soc64-firewall.h
@@ -9,6 +9,8 @@
 
 #include <linux/bitops.h>
 
+#include <mach/socfpga/soc64-regs.h>
+
 struct socfpga_firwall_l4_per {
 	u32	nand;		/* 0x00 */
 	u32	nand_data;

-- 
2.47.3

[PATCH 2/6] arm: socfgpa: agilex5: remove mailbox_s10 from barebox proper

[Michael Tretter]

The mailbox_s10 is only used to retrieve the QSPI configuration from the
SDM. The barebox PBL retrieves this configuration and stores the result
in a handover register. barebox proper retrieves the status from the
handover register and doesn't interact with the SDM via mailbox_s10 get.

Thus, remove malbox_s10 from barebox proper, since it's not used there.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c54d2a289341..6a8117874136 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -24,7 +24,6 @@ pbl-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += soc64-system-manager.o \
 				atf.o
 
 obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += secure_reg_helper.o \
-			        mailbox_s10.o \
 				      smc_api.o
 
 ifdef CONFIG_ARCH_SOCFPGA_CYCLONE5

-- 
2.47.3

[PATCH 3/6] arm: socfpga: agilex5: extract function to request qspi access

[Michael Tretter]

Requesting access to the QSPI flash access may actually fail due to the
firmware configuration. Tell the user about the failure, since other
features, for example, barebox environment in flash, may rely on QSPI
flash access.

Extract a helper function and print a warning, if QSPI flash access was
not granted.

Since requesting QSPI flash access is currently the only function that
uses the S10 mailbox, move socfgpa_mailbox_s10_init(), too.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/atf.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/atf.c b/arch/arm/mach-socfpga/atf.c
index c7be4e11d2ea..3719bde0e8bb 100644
--- a/arch/arm/mach-socfpga/atf.c
+++ b/arch/arm/mach-socfpga/atf.c
@@ -12,6 +12,23 @@
 #include <mach/socfpga/soc64-sdram.h>
 #include <mach/socfpga/soc64-system-manager.h>
 
+static void socfpga_agilex5_qspi_init(void)
+{
+	int ret;
+
+	ret = socfpga_mailbox_s10_init();
+	if (ret) {
+		pr_warn("Failed to init s10 mailbox: %d\n", ret);
+		return;
+	}
+
+	ret = socfpga_mailbox_s10_qspi_open();
+	if (ret) {
+		pr_warn("Failed to request QSPI access: %d\n", ret);
+		return;
+	}
+}
+
 static void __noreturn agilex5_load_and_start_image_via_tfa(void)
 {
 	void *bl31 = (void *)AGILEX5_ATF_BL31_BASE_ADDR;
@@ -55,8 +72,7 @@ void __noreturn agilex5_barebox_entry(void *fdt)
 			writel(LCR_BKSE, SOCFPGA_UART0_ADDRESS + LCR);
 		agilex5_ddr_init_full();
 
-		socfpga_mailbox_s10_init();
-		socfpga_mailbox_s10_qspi_open();
+		socfpga_agilex5_qspi_init();
 
 		agilex5_load_and_start_image_via_tfa();
 		__builtin_unreachable();

-- 
2.47.3

[PATCH 4/6] arm: socfpga: mailbox_s10: keep clock rate in Hz

[Michael Tretter]

The QSPI reference clock rate is retrieved in Hz from the firmware, but
stored in kHz in a handover register.

Initially, the clock rated is stored as Hz in clk_khz, and later
converted to kHz before printing and storing it. Initially the warning
prints the clock rate in Hz, but prints kHz as unit. This is confusing.

Leave the clock rate in Hz, and convert it to kHz when used.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/mailbox_s10.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 4199c4fb913a..c6ea081165d4 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -300,7 +300,7 @@ int socfpga_mailbox_s10_qspi_open(void)
 	u32 resp_buf[1] = {};
 	u32 resp_buf_len = ARRAY_SIZE(resp_buf);
 	u32 reg;
-	u32 clk_khz;
+	u32 clk_rate;
 	int try = 0;
 
 retry:
@@ -331,20 +331,19 @@ int socfpga_mailbox_s10_qspi_open(void)
 	}
 
 	/* Get the QSPI clock from SDM response and save for later use */
-	clk_khz = resp_buf[0];
-	if (clk_khz < 1000) {
-		pr_err("QSPI: Unexpected reference clock rate: %d kHz\n",
-		       clk_khz);
+	clk_rate = resp_buf[0];
+	if (clk_rate < 1000) {
+		pr_err("QSPI: Unexpected reference clock rate: %d Hz\n",
+		       clk_rate);
 		return -EINVAL;
 	}
 
-	clk_khz /= 1000;
-	pr_info("QSPI: reference clock at %d kHz\n", clk_khz);
+	pr_info("QSPI: reference clock at %d kHz\n", clk_rate / 1000);
 
 	reg = (readl(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
 			~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
 
-	writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg,
+	writel(((clk_rate / 1000) & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg,
 	       SOCFPGA_SYSMGR_ADDRESS + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
 
 	return 0;

-- 
2.47.3

[PATCH 5/6] arm: socfpga: mailbox_s10: add write_qspi_refclk helper

[Michael Tretter]

Add a helper function that hides the actually used register, field, and
format. This makes the code easier to read and allows to move it to a
better location.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/mailbox_s10.c         |  9 +++------
 include/mach/socfpga/soc64-system-manager.h | 21 +++++++++++++++++++++
 2 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index c6ea081165d4..417816673c3d 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -299,7 +299,6 @@ int socfpga_mailbox_s10_qspi_open(void)
 	int ret;
 	u32 resp_buf[1] = {};
 	u32 resp_buf_len = ARRAY_SIZE(resp_buf);
-	u32 reg;
 	u32 clk_rate;
 	int try = 0;
 
@@ -340,11 +339,9 @@ int socfpga_mailbox_s10_qspi_open(void)
 
 	pr_info("QSPI: reference clock at %d kHz\n", clk_rate / 1000);
 
-	reg = (readl(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
-			~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
-
-	writel(((clk_rate / 1000) & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg,
-	       SOCFPGA_SYSMGR_ADDRESS + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+	ret = socfpga_agilex5_write_qspi_refclk(clk_rate);
+	if (ret)
+		return ret;
 
 	return 0;
 
diff --git a/include/mach/socfpga/soc64-system-manager.h b/include/mach/socfpga/soc64-system-manager.h
index 862e974b1902..a5df69855a28 100644
--- a/include/mach/socfpga/soc64-system-manager.h
+++ b/include/mach/socfpga/soc64-system-manager.h
@@ -8,6 +8,8 @@
 
 #include <linux/bitops.h>
 
+#include <mach/socfpga/soc64-regs.h>
+
 #define SYSMGR_SOC64_SILICONID_1		0x00
 #define SYSMGR_SOC64_SILICONID_2		0x04
 #define SYSMGR_SOC64_WDDBG			0x08
@@ -173,4 +175,23 @@ void agilex5_security_interleaving_off(void);
 void agilex5_initialize_security_policies(void);
 void agilex5_sysmgr_pinmux_init(void);
 
+static inline int socfpga_agilex5_write_qspi_refclk(unsigned long clkrate)
+{
+	unsigned long clkrate_khz;
+	u32 reg;
+
+	/* Follow U-Boot and store clock rate in kHz */
+	clkrate_khz = clkrate / 1000;
+	if (clkrate_khz & ~SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK)
+		return -EINVAL;
+
+	reg = readl(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+	reg &= ~SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK;
+	reg |= (SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK & clkrate_khz);
+
+	writel(reg, SOCFPGA_SYSMGR_ADDRESS + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+
+	return 0;
+}
+
 #endif /* _SOC64_SYSTEM_MANAGER_H_ */

-- 
2.47.3

[PATCH 6/6] arm: socfpga: agilex5: extract write_qspi_refclk from mailbox

[Michael Tretter]

Currently, the QSPI reference clock rate is stored to a register as a
side effect of requesting access to the QSPI flash via mailbox. This is
surprising and inconvenient.

Return the QSPI reference clock rate to the calling function that
requested QSPI flash access and let the caller decide what to do with
it.

This detangles the mailbox code and the low level code, and eventually
allows to use the clock rate in low level platform code.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/mach-socfpga/atf.c         | 9 ++++++++-
 arch/arm/mach-socfpga/mailbox_s10.c | 7 ++-----
 include/mach/socfpga/mailbox_s10.h  | 2 +-
 3 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-socfpga/atf.c b/arch/arm/mach-socfpga/atf.c
index 3719bde0e8bb..e1f0a3558b04 100644
--- a/arch/arm/mach-socfpga/atf.c
+++ b/arch/arm/mach-socfpga/atf.c
@@ -14,6 +14,7 @@
 
 static void socfpga_agilex5_qspi_init(void)
 {
+	unsigned long master_ref_clk = 0;
 	int ret;
 
 	ret = socfpga_mailbox_s10_init();
@@ -22,11 +23,17 @@ static void socfpga_agilex5_qspi_init(void)
 		return;
 	}
 
-	ret = socfpga_mailbox_s10_qspi_open();
+	ret = socfpga_mailbox_s10_qspi_open(&master_ref_clk);
 	if (ret) {
 		pr_warn("Failed to request QSPI access: %d\n", ret);
 		return;
 	}
+
+	ret = socfpga_agilex5_write_qspi_refclk(master_ref_clk);
+	if (ret) {
+		pr_warn("Failed to store reference clock: %d\n", ret);
+		return;
+	}
 }
 
 static void __noreturn agilex5_load_and_start_image_via_tfa(void)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 417816673c3d..fdbd7f272866 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -10,7 +10,6 @@
 #include <io.h>
 #include <mach/socfpga/mailbox_s10.h>
 #include <mach/socfpga/soc64-regs.h>
-#include <mach/socfpga/soc64-system-manager.h>
 
 #define MBOX_READL(reg)			\
 	 readl(SOCFPGA_MAILBOX_ADDRESS + (reg))
@@ -294,7 +293,7 @@ int socfpga_mailbox_s10_qspi_close(void)
 			     0, NULL, 0, 0, NULL);
 }
 
-int socfpga_mailbox_s10_qspi_open(void)
+int socfpga_mailbox_s10_qspi_open(unsigned long *master_ref_clk)
 {
 	int ret;
 	u32 resp_buf[1] = {};
@@ -339,9 +338,7 @@ int socfpga_mailbox_s10_qspi_open(void)
 
 	pr_info("QSPI: reference clock at %d kHz\n", clk_rate / 1000);
 
-	ret = socfpga_agilex5_write_qspi_refclk(clk_rate);
-	if (ret)
-		return ret;
+	*master_ref_clk = clk_rate;
 
 	return 0;
 
diff --git a/include/mach/socfpga/mailbox_s10.h b/include/mach/socfpga/mailbox_s10.h
index bba4adbbe877..0033bf40d45b 100644
--- a/include/mach/socfpga/mailbox_s10.h
+++ b/include/mach/socfpga/mailbox_s10.h
@@ -185,7 +185,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
 int socfpga_mailbox_s10_init(void);
 
 int socfpga_mailbox_s10_qspi_close(void);
-int socfpga_mailbox_s10_qspi_open(void);
+int socfpga_mailbox_s10_qspi_open(unsigned long *master_ref_clk);
 int socfpga_mailbox_s10_qspi_get_device_info(u32 *resp_buf, u32 resp_buf_len);
 
 #endif /* _MAILBOX_S10_H_ */

-- 
2.47.3

Re: [PATCH 0/6] arm: socfpga: agilex5: cleanup QSPI flash low level code

[Sascha Hauer]

On Wed, 06 May 2026 11:06:06 +0200, Michael Tretter wrote:
> On Agilex 5, barebox runs in the HPS (hard processor system) which needs
> to explicitly request QSPI flash access from the SDM (secure device
> manager). This request may be denied by the SDM. Furthermore, barebox
> needs to store the clock rate reported by the SDM.
> 
> Cleanup and refactor the code that handles the QSPI flash request from
> the SDM. This is a preparation for eventually reading a second stage
> boot loader from QSPI flash.
> 
> [...]

Applied, thanks!

[1/6] arm: socfpga: agilex5: add missing include soc64-regs.h
      https://git.pengutronix.de/cgit/barebox/commit/?id=1f4a856e0936 (link may not be stable)
[2/6] arm: socfgpa: agilex5: remove mailbox_s10 from barebox proper
      https://git.pengutronix.de/cgit/barebox/commit/?id=dc418389064d (link may not be stable)
[3/6] arm: socfpga: agilex5: extract function to request qspi access
      https://git.pengutronix.de/cgit/barebox/commit/?id=87a298eab713 (link may not be stable)
[4/6] arm: socfpga: mailbox_s10: keep clock rate in Hz
      https://git.pengutronix.de/cgit/barebox/commit/?id=2ee06bcf5410 (link may not be stable)
[5/6] arm: socfpga: mailbox_s10: add write_qspi_refclk helper
      https://git.pengutronix.de/cgit/barebox/commit/?id=5998c5c1b3ee (link may not be stable)
[6/6] arm: socfpga: agilex5: extract write_qspi_refclk from mailbox
      https://git.pengutronix.de/cgit/barebox/commit/?id=11daf34fa202 (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>