[PATCH] clk: rockchip: Fix error pointer check after rockchip_clk_register_gate_link()

[PATCH] clk: rockchip: Fix error pointer check after rockchip_clk_register_gate_link()

[Alexander Shiyan]

From: Miaoqian Lin <linmq006@gmail.com>

Replace NULL check with IS_ERR_OR_NULL() check after calling
rockchip_clk_register_gate_link() since this function
returns error pointers (ERR_PTR).

Fixes: c62fa612cfa6 ("clk: rockchip: implement linked gate clock support")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://patch.msgid.link/20250805030358.3665878-1-linmq006@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 drivers/clk/rockchip/clk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 987c3bc518..d01574c60b 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -566,7 +566,7 @@ void rockchip_clk_register_late_branches(struct device *dev,
 			break;
 		}
 
-		if (!pdev)
+		if (IS_ERR_OR_NULL(pdev))
 			dev_err(dev, "failed to register device for clock %s\n", list->name);
 	}
 }
-- 
2.52.0

[PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Alexander Shiyan]

From: Shawn Lin <shawn.lin@rock-chips.com>

The PCIe pipe clocks are currently left as orphan clocks and remain
enabled indefinitely, which is suboptimal. Add the missing clock gates
so the PCIe driver can explicitly manage them when not in use. In order
not to break compatibility with old DTB, mark them as CLK_IGNORE_UNUSED.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/1772799641-32164-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 drivers/clk/rockchip/clk-rk3568.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 3b0cfdb865..12b3514afb 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -830,6 +830,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 			RK3568_CLKGATE_CON(12), 3, GFLAGS),
 	GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
 			RK3568_CLKGATE_CON(12), 4, GFLAGS),
+	GATE(CLK_PCIE20_PIPE_DFT, "clk_pcie20_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
+			RK3568_CLKGATE_CON(12), 5, GFLAGS),
 	GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
 			RK3568_CLKGATE_CON(12), 8, GFLAGS),
 	GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
@@ -840,6 +842,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 			RK3568_CLKGATE_CON(12), 11, GFLAGS),
 	GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
 			RK3568_CLKGATE_CON(12), 12, GFLAGS),
+	GATE(CLK_PCIE30X1_PIPE_DFT, "clk_pcie30x1_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
+			RK3568_CLKGATE_CON(12), 13, GFLAGS),
 	GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
 			RK3568_CLKGATE_CON(13), 0, GFLAGS),
 	GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
@@ -850,6 +854,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 			RK3568_CLKGATE_CON(13), 3, GFLAGS),
 	GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
 			RK3568_CLKGATE_CON(13), 4, GFLAGS),
+	GATE(CLK_PCIE30X2_PIPE_DFT, "clk_pcie30x2_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
+			RK3568_CLKGATE_CON(13), 5, GFLAGS),
 	GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
 			RK3568_CLKGATE_CON(11), 0, GFLAGS),
 	GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
-- 
2.52.0

Re: [PATCH] clk: rockchip: Fix error pointer check after rockchip_clk_register_gate_link()

[Sascha Hauer]

Hi Alexander,

On 2026-05-28 15:15, Alexander Shiyan wrote:
> From: Miaoqian Lin <linmq006@gmail.com>
> 
> Replace NULL check with IS_ERR_OR_NULL() check after calling
> rockchip_clk_register_gate_link() since this function
> returns error pointers (ERR_PTR).
> 
> Fixes: c62fa612cfa6 ("clk: rockchip: implement linked gate clock support")
> Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
> Link: https://patch.msgid.link/20250805030358.3665878-1-linmq006@gmail.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
> ---
>  drivers/clk/rockchip/clk.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks.

BTW better quote the whole Linux commit message including the tags and
make yourself the author of the patch. The original Linux commit authors
and reviewers are likely not interested in that the patch is merged in
barebox. Also when the original patch carries a reviewed-by: tag this
is only valid in the Linux context, not in barebox.

Sascha


> 
> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
> index 987c3bc518..d01574c60b 100644
> --- a/drivers/clk/rockchip/clk.c
> +++ b/drivers/clk/rockchip/clk.c
> @@ -566,7 +566,7 @@ void rockchip_clk_register_late_branches(struct device *dev,
>  			break;
>  		}
>  
> -		if (!pdev)
> +		if (IS_ERR_OR_NULL(pdev))
>  			dev_err(dev, "failed to register device for clock %s\n", list->name);
>  	}
>  }
> -- 
> 2.52.0
> 
> 
> 

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Re: (subset) [PATCH] clk: rockchip: Fix error pointer check after rockchip_clk_register_gate_link()

[Sascha Hauer]

On Thu, 28 May 2026 15:15:30 +0300, Alexander Shiyan wrote:
> Replace NULL check with IS_ERR_OR_NULL() check after calling
> rockchip_clk_register_gate_link() since this function
> returns error pointers (ERR_PTR).
> 
> 

Applied, thanks!

[1/1] clk: rockchip: Fix error pointer check after rockchip_clk_register_gate_link()
      https://git.pengutronix.de/cgit/barebox/commit/?id=6a11a80667cd (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>

Re: [PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Sascha Hauer]

On Thu, 28 May 2026 15:15:31 +0300, Alexander Shiyan wrote:
> The PCIe pipe clocks are currently left as orphan clocks and remain
> enabled indefinitely, which is suboptimal. Add the missing clock gates
> so the PCIe driver can explicitly manage them when not in use. In order
> not to break compatibility with old DTB, mark them as CLK_IGNORE_UNUSED.
> 
> 

Applied, thanks!

[1/1] clk: rockchip: rk3568: Add PCIe pipe clock gates
      https://git.pengutronix.de/cgit/barebox/commit/?id=28f3a11c9a73 (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>

Re: [PATCH] clk: rockchip: rk3568: Add PCIe pipe clock gates

[Sascha Hauer]

On Thu, 28 May 2026 15:15:31 +0300, Alexander Shiyan wrote:
> The PCIe pipe clocks are currently left as orphan clocks and remain
> enabled indefinitely, which is suboptimal. Add the missing clock gates
> so the PCIe driver can explicitly manage them when not in use. In order
> not to break compatibility with old DTB, mark them as CLK_IGNORE_UNUSED.
> 
> 

Applied, thanks!

[1/1] clk: rockchip: rk3568: Add PCIe pipe clock gates
      https://git.pengutronix.de/cgit/barebox/commit/?id=28f3a11c9a73 (link may not be stable)

Best regards,
-- 
Sascha Hauer <s.hauer@pengutronix.de>