[PATCH 0/7] net: phy: dp83867: cleanup and link downshift support

[PATCH 0/7] net: phy: dp83867: cleanup and link downshift support

[Michael Tretter]

Hello,

the dp83867 network phy supports link downshift, if a gigabit link cannot be
established. For example, this can happen if the cabling does not support
gigabit Ethernet.

This series enables the downshift by default (Linux also enables it by
default). Additionally, the link status is read from the dp83867-specific
register to take the possible downshift into account when reporting the link
speed.

Furthermore, the series contains a handful of cleanup patches.

Michael

Michael Tretter (3):
  net: phy: dp83867: convert driver to spdx
  net: phy: dp83867: fix checkpatch checks and warnings
  net: phy: dp83867: remove useless call to genphy_config_aneg

Thomas Haemmerle (4):
  net: phy: dp83867: simplify dp83867_config_init
  net: phy: dp83867: remove explicit setting of cfg2
  net: phy: dp83867: read status from PHY status register PHYSTS
  net: phy: dp83867: enable link downshift by default

 drivers/net/phy/dp83867.c | 169 ++++++++++++++++++++------------------
 1 file changed, 90 insertions(+), 79 deletions(-)

-- 
2.29.2


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 1/7] net: phy: dp83867: convert driver to spdx

[Michael Tretter]

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/net/phy/dp83867.c | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 8131e8c9d6c6..153b60def320 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Driver for the Texas Instruments DP83867 PHY
  *
  * Copyright (C) 2015 Texas Instruments Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #include <common.h>
-- 
2.29.2


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 2/7] net: phy: dp83867: fix checkpatch checks and warnings

[Michael Tretter]

Mostly indentation changes to make checkpatch happy and make the code a
bit easier to the eyes.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/net/phy/dp83867.c | 75 +++++++++++++++++++--------------------
 1 file changed, 37 insertions(+), 38 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 153b60def320..deee7e3ae7ca 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -111,7 +111,7 @@ struct dp83867_private {
 
 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 {
-	struct dp83867_private *dp83867 = (struct dp83867_private *)phydev->priv;
+	struct dp83867_private *dp83867 = phydev->priv;
 	u16 val;
 
 	val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR);
@@ -146,18 +146,18 @@ static int dp83867_of_init(struct phy_device *phydev)
 
 	dp83867->rxctrl_strap_quirk =
 			of_property_read_bool(of_node,
-					"ti,dp83867-rxctrl-strap-quirk");
+					      "ti,dp83867-rxctrl-strap-quirk");
 
 	ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
-			&dp83867->rx_id_delay);
+				   &dp83867->rx_id_delay);
 	if (ret && (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-			phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
+		    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 		return ret;
 
 	ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
-			&dp83867->tx_id_delay);
+				   &dp83867->tx_id_delay);
 	if (ret && (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-			phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
+		    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 		return ret;
 
 	if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
@@ -167,13 +167,13 @@ static int dp83867_of_init(struct phy_device *phydev)
 		dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 
 	return of_property_read_u32(of_node, "ti,fifo-depth",
-			&dp83867->fifo_depth);
+				    &dp83867->fifo_depth);
 }
 
 static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
 {
 	return phydev->interface == PHY_INTERFACE_MODE_SGMII ||
-			phydev->interface == PHY_INTERFACE_MODE_QSGMII;
+	       phydev->interface == PHY_INTERFACE_MODE_QSGMII;
 }
 
 static int dp83867_config_init(struct phy_device *phydev)
@@ -192,7 +192,7 @@ static int dp83867_config_init(struct phy_device *phydev)
 		if (ret)
 			return ret;
 	} else {
-		dp83867 = (struct dp83867_private *)phydev->priv;
+		dp83867 = phydev->priv;
 	}
 
 	/* Restart the PHY.  */
@@ -201,22 +201,21 @@ static int dp83867_config_init(struct phy_device *phydev)
 
 	if (dp83867->rxctrl_strap_quirk) {
 		val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
-				DP83867_DEVADDR);
+					    DP83867_DEVADDR);
 		val &= ~BIT(7);
-		phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
-				val);
+		phy_write_mmd_indirect(phydev, DP83867_CFG4,
+				       DP83867_DEVADDR, val);
 	}
 
 	if (phy_interface_is_rgmii(phydev)) {
 		val = DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER |
-			dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT;
+		      dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT;
 		ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 		if (ret)
 			return ret;
 	} else if (phy_interface_is_sgmii(phydev)) {
-		phy_write(phydev, MII_BMCR, BMCR_ANENABLE |
-				BMCR_FULLDPLX |
-				BMCR_SPEED1000);
+		phy_write(phydev, MII_BMCR,
+			  BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000);
 
 		cfg2 = phy_read(phydev, MII_DP83867_CFG2);
 		cfg2 &= MII_DP83867_CFG2_MASK;
@@ -229,12 +228,12 @@ static int dp83867_config_init(struct phy_device *phydev)
 		phy_write(phydev, MII_DP83867_CFG2, cfg2);
 
 		phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
-				DP83867_DEVADDR, 0x0);
+				       DP83867_DEVADDR, 0x0);
 
 		val = DP83867_PHYCTRL_SGMIIEN |
-			DP83867_MDI_CROSSOVER_MDIX << DP83867_MDI_CROSSOVER |
-			dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT |
-			dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT;
+		      DP83867_MDI_CROSSOVER_MDIX << DP83867_MDI_CROSSOVER |
+		      dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT |
+		      dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT;
 
 		phy_write(phydev, MII_DP83867_PHYCTRL, val);
 		phy_write(phydev, MII_DP83867_BISCR, 0x0);
@@ -242,12 +241,12 @@ static int dp83867_config_init(struct phy_device *phydev)
 
 	if (phy_interface_is_rgmii(phydev)) {
 		val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
-				DP83867_DEVADDR);
+					    DP83867_DEVADDR);
 
 		switch (phydev->interface) {
 		case PHY_INTERFACE_MODE_RGMII_ID:
-			val |= (DP83867_RGMII_TX_CLK_DELAY_EN
-					| DP83867_RGMII_RX_CLK_DELAY_EN);
+			val |= DP83867_RGMII_TX_CLK_DELAY_EN |
+			       DP83867_RGMII_RX_CLK_DELAY_EN;
 			break;
 		case PHY_INTERFACE_MODE_RGMII_TXID:
 			val |= DP83867_RGMII_TX_CLK_DELAY_EN;
@@ -259,23 +258,23 @@ static int dp83867_config_init(struct phy_device *phydev)
 			break;
 		}
 		phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
-				DP83867_DEVADDR, val);
+				       DP83867_DEVADDR, val);
 
 		delay = (dp83867->rx_id_delay |
 			(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 
 		phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
-				DP83867_DEVADDR, delay);
+				       DP83867_DEVADDR, delay);
 
 		if (dp83867->io_impedance >= 0) {
 			val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
-					DP83867_DEVADDR);
+						    DP83867_DEVADDR);
 			val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
-			val |= dp83867->io_impedance
-					& DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
+			val |= (dp83867->io_impedance &
+				DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
 
 			phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
-					DP83867_DEVADDR, val);
+					       DP83867_DEVADDR, val);
 		}
 	}
 
@@ -290,17 +289,17 @@ static int dp83867_config_init(struct phy_device *phydev)
 }
 
 static struct phy_driver dp83867_driver[] = {
-		{
-			.phy_id = DP83867_PHY_ID,
-			.phy_id_mask = 0xfffffff0,
-			.drv.name = "TI DP83867",
-			.features = PHY_GBIT_FEATURES,
+	{
+		.phy_id = DP83867_PHY_ID,
+		.phy_id_mask = 0xfffffff0,
+		.drv.name = "TI DP83867",
+		.features = PHY_GBIT_FEATURES,
 
-			.config_init = dp83867_config_init,
+		.config_init = dp83867_config_init,
 
-			.config_aneg = genphy_config_aneg,
-			.read_status = genphy_read_status,
-		},
+		.config_aneg = genphy_config_aneg,
+		.read_status = genphy_read_status,
+	},
 };
 
 device_phy_drivers(dp83867_driver);
-- 
2.29.2


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 3/7] net: phy: dp83867: remove useless call to genphy_config_aneg

[Michael Tretter]

genphy_config_aneg will be called by the generic code anyway. No need to
call it from the driver.

As at it, do not explicitly set the config_aneg and read_status
pointers, because they will be automatically set anyway.

Remove the "hello world" message by the driver, too.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/net/phy/dp83867.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index deee7e3ae7ca..8a14927071b9 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -278,13 +278,9 @@ static int dp83867_config_init(struct phy_device *phydev)
 		}
 	}
 
-	genphy_config_aneg(phydev);
-
 	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 		dp83867_config_port_mirroring(phydev);
 
-	dev_info(&phydev->dev, "DP83867\n");
-
 	return 0;
 }
 
@@ -294,11 +290,7 @@ static struct phy_driver dp83867_driver[] = {
 		.phy_id_mask = 0xfffffff0,
 		.drv.name = "TI DP83867",
 		.features = PHY_GBIT_FEATURES,
-
 		.config_init = dp83867_config_init,
-
-		.config_aneg = genphy_config_aneg,
-		.read_status = genphy_read_status,
 	},
 };
 
-- 
2.29.2


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 4/7] net: phy: dp83867: simplify dp83867_config_init

[Michael Tretter]

From: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>

Reorder the code in dp83867_config_init to remove duplicated check of
the phy interface.

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/net/phy/dp83867.c | 49 ++++++++++++++++++---------------------
 1 file changed, 23 insertions(+), 26 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 8a14927071b9..e796498c4a18 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -213,33 +213,7 @@ static int dp83867_config_init(struct phy_device *phydev)
 		ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 		if (ret)
 			return ret;
-	} else if (phy_interface_is_sgmii(phydev)) {
-		phy_write(phydev, MII_BMCR,
-			  BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000);
-
-		cfg2 = phy_read(phydev, MII_DP83867_CFG2);
-		cfg2 &= MII_DP83867_CFG2_MASK;
-		cfg2 |= MII_DP83867_CFG2_SPEEDOPT_10EN |
-			MII_DP83867_CFG2_SGMII_AUTONEGEN |
-			MII_DP83867_CFG2_SPEEDOPT_ENH |
-			MII_DP83867_CFG2_SPEEDOPT_CNT |
-			MII_DP83867_CFG2_SPEEDOPT_INTLOW;
-
-		phy_write(phydev, MII_DP83867_CFG2, cfg2);
-
-		phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
-				       DP83867_DEVADDR, 0x0);
-
-		val = DP83867_PHYCTRL_SGMIIEN |
-		      DP83867_MDI_CROSSOVER_MDIX << DP83867_MDI_CROSSOVER |
-		      dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT |
-		      dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT;
-
-		phy_write(phydev, MII_DP83867_PHYCTRL, val);
-		phy_write(phydev, MII_DP83867_BISCR, 0x0);
-	}
 
-	if (phy_interface_is_rgmii(phydev)) {
 		val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
 					    DP83867_DEVADDR);
 
@@ -276,6 +250,29 @@ static int dp83867_config_init(struct phy_device *phydev)
 			phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
 					       DP83867_DEVADDR, val);
 		}
+	} else if (phy_interface_is_sgmii(phydev)) {
+		phy_write(phydev, MII_BMCR,
+			  BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000);
+
+		cfg2 = phy_read(phydev, MII_DP83867_CFG2);
+		cfg2 &= MII_DP83867_CFG2_MASK;
+		cfg2 |= MII_DP83867_CFG2_SPEEDOPT_10EN |
+			MII_DP83867_CFG2_SGMII_AUTONEGEN |
+			MII_DP83867_CFG2_SPEEDOPT_ENH |
+			MII_DP83867_CFG2_SPEEDOPT_CNT |
+			MII_DP83867_CFG2_SPEEDOPT_INTLOW;
+		phy_write(phydev, MII_DP83867_CFG2, cfg2);
+
+		phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
+				       DP83867_DEVADDR, 0x0);
+
+		val = DP83867_PHYCTRL_SGMIIEN |
+		      DP83867_MDI_CROSSOVER_MDIX << DP83867_MDI_CROSSOVER |
+		      dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT |
+		      dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT;
+
+		phy_write(phydev, MII_DP83867_PHYCTRL, val);
+		phy_write(phydev, MII_DP83867_BISCR, 0x0);
 	}
 
 	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
-- 
2.29.2


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 5/7] net: phy: dp83867: remove explicit setting of cfg2

[Michael Tretter]

From: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>

Setting cfg2 is superfluous, because it just sets the default value.
Remove it.

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/net/phy/dp83867.c | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index e796498c4a18..dd769b4d3e38 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -180,7 +180,7 @@ static int dp83867_config_init(struct phy_device *phydev)
 {
 	struct dp83867_private *dp83867;
 	int ret;
-	u16 val, delay, cfg2;
+	u16 val, delay;
 
 	if (!phydev->priv) {
 		dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
@@ -254,15 +254,6 @@ static int dp83867_config_init(struct phy_device *phydev)
 		phy_write(phydev, MII_BMCR,
 			  BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000);
 
-		cfg2 = phy_read(phydev, MII_DP83867_CFG2);
-		cfg2 &= MII_DP83867_CFG2_MASK;
-		cfg2 |= MII_DP83867_CFG2_SPEEDOPT_10EN |
-			MII_DP83867_CFG2_SGMII_AUTONEGEN |
-			MII_DP83867_CFG2_SPEEDOPT_ENH |
-			MII_DP83867_CFG2_SPEEDOPT_CNT |
-			MII_DP83867_CFG2_SPEEDOPT_INTLOW;
-		phy_write(phydev, MII_DP83867_CFG2, cfg2);
-
 		phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 				       DP83867_DEVADDR, 0x0);
 
-- 
2.29.2


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 6/7] net: phy: dp83867: read status from PHY status register PHYSTS

[Michael Tretter]

From: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>

Read link status information in dp83867 specific register instead of
using `genphy_read_status()`.

In case of a link downshift, `genphy_read_status()` can return
`SPEED_1000` even if the negotiated speed is 100 Mbit.

A downshift can happen, if both link-partners are gigabit-capable, but
the connection supports only 100 MBit, for example because of a 100 MBit
PoE injector that connects only 2 of the 4 twisted pairs.

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/net/phy/dp83867.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index dd769b4d3e38..c19f6ecba267 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -16,6 +16,7 @@
 #define DP83867_DEVADDR		MDIO_MMD_VEND2
 
 #define MII_DP83867_PHYCTRL	0x10
+#define MII_DP83867_PHYSTS	0x11
 #define MII_DP83867_MICR	0x12
 #define MII_DP83867_ISR		0x13
 #define MII_DP83867_CFG2	0x14
@@ -65,6 +66,11 @@
 #define DP83867_PHYCTRL_TXFIFO_SHIFT		14
 #define DP83867_PHYCR_RESERVED_MASK		BIT(11)
 
+/* PHY STS bits */
+#define DP83867_PHYSTS_SPEED_1000		BIT(15)
+#define DP83867_PHYSTS_SPEED_100		BIT(14)
+#define DP83867_PHYSTS_DUPLEX_FULL		BIT(13)
+
 /* RGMIIDCTL bits */
 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT	4
 
@@ -109,6 +115,35 @@ struct dp83867_private {
 	bool rxctrl_strap_quirk;
 };
 
+static int dp83867_read_status(struct phy_device *phydev)
+{
+	int status;
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	status = phy_read(phydev, MII_DP83867_PHYSTS);
+	if (status < 0)
+		return status;
+
+	phydev->speed = SPEED_10;
+	phydev->duplex = DUPLEX_HALF;
+
+	if (status & DP83867_PHYSTS_SPEED_1000)
+		phydev->speed = SPEED_1000;
+	else if (status & DP83867_PHYSTS_SPEED_100)
+		phydev->speed = SPEED_100;
+
+	if (status & DP83867_PHYSTS_DUPLEX_FULL)
+		phydev->duplex = DUPLEX_FULL;
+
+	phydev->pause = phydev->asym_pause = 0;
+
+	return 0;
+}
+
 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 {
 	struct dp83867_private *dp83867 = phydev->priv;
@@ -279,6 +314,7 @@ static struct phy_driver dp83867_driver[] = {
 		.drv.name = "TI DP83867",
 		.features = PHY_GBIT_FEATURES,
 		.config_init = dp83867_config_init,
+		.read_status = dp83867_read_status,
 	},
 };
 
-- 
2.29.2


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

[PATCH 7/7] net: phy: dp83867: enable link downshift by default

[Michael Tretter]

From: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>

Linux enables link downshift by default. Use the same bit definitions as
Linux and enable downshift in Barebox, as well.

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/net/phy/dp83867.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index c19f6ecba267..05af83f076a8 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -75,12 +75,12 @@
 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT	4
 
 /* CFG2 bits */
-#define MII_DP83867_CFG2_SPEEDOPT_10EN		0x0040
-#define MII_DP83867_CFG2_SGMII_AUTONEGEN	0x0080
-#define MII_DP83867_CFG2_SPEEDOPT_ENH		0x0100
-#define MII_DP83867_CFG2_SPEEDOPT_CNT		0x0800
-#define MII_DP83867_CFG2_SPEEDOPT_INTLOW	0x2000
-#define MII_DP83867_CFG2_MASK			0x003F
+#define DP83867_DOWNSHIFT_EN			(BIT(8) | BIT(9))
+#define DP83867_DOWNSHIFT_ATTEMPT_MASK		(BIT(10) | BIT(11))
+#define DP83867_DOWNSHIFT_1_COUNT_VAL		0
+#define DP83867_DOWNSHIFT_2_COUNT_VAL		1
+#define DP83867_DOWNSHIFT_4_COUNT_VAL		2
+#define DP83867_DOWNSHIFT_8_COUNT_VAL		3
 
 /* CFG4 bits */
 #define DP83867_CFG4_SGMII_AUTONEG_TIMER_MASK	0x60
@@ -301,6 +301,10 @@ static int dp83867_config_init(struct phy_device *phydev)
 		phy_write(phydev, MII_DP83867_BISCR, 0x0);
 	}
 
+	val = phy_read(phydev, MII_DP83867_CFG2);
+	val |= DP83867_DOWNSHIFT_EN;
+	phy_write(phydev, MII_DP83867_CFG2, val);
+
 	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 		dp83867_config_port_mirroring(phydev);
 
-- 
2.29.2


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 0/7] net: phy: dp83867: cleanup and link downshift support

[Sascha Hauer]

On Fri, Mar 19, 2021 at 02:10:09PM +0100, Michael Tretter wrote:
> Hello,
> 
> the dp83867 network phy supports link downshift, if a gigabit link cannot be
> established. For example, this can happen if the cabling does not support
> gigabit Ethernet.
> 
> This series enables the downshift by default (Linux also enables it by
> default). Additionally, the link status is read from the dp83867-specific
> register to take the possible downshift into account when reporting the link
> speed.
> 
> Furthermore, the series contains a handful of cleanup patches.
> 
> Michael

Applied, thanks

Sascha

> 
> Michael Tretter (3):
>   net: phy: dp83867: convert driver to spdx
>   net: phy: dp83867: fix checkpatch checks and warnings
>   net: phy: dp83867: remove useless call to genphy_config_aneg
> 
> Thomas Haemmerle (4):
>   net: phy: dp83867: simplify dp83867_config_init
>   net: phy: dp83867: remove explicit setting of cfg2
>   net: phy: dp83867: read status from PHY status register PHYSTS
>   net: phy: dp83867: enable link downshift by default
> 
>  drivers/net/phy/dp83867.c | 169 ++++++++++++++++++++------------------
>  1 file changed, 90 insertions(+), 79 deletions(-)
> 
> -- 
> 2.29.2
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox