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From: Antony Pavlov <antonynpavlov@gmail.com>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH v2 01/11] clocksource: timer-riscv: select CSR from device tree
Date: Fri,  7 May 2021 01:08:24 +0300	[thread overview]
Message-ID: <20210506220834.223350-2-antonynpavlov@gmail.com> (raw)
In-Reply-To: <20210506220834.223350-1-antonynpavlov@gmail.com>

barebox timer-riscv driver supports one of user counters:

  * 'cycle', counter for RDCYCLE instruction (CSR 0xc00);
  * 'time', timer for RDTIME instruction (CSR 0xc01).

At the moment in S-mode timer-riscv uses the 'cycle' counter,
and in M-mode timer-riscv uses the 'time' timer.

Alas picorv32 CPU core supports only the 'cycle' counter.
VexRiscV CPU core supports only the 'time' timer.

This patch makes it possible to use the 'time' timer
for VexRiscV CPU in M-mode.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/riscv/cpu/time.c             |  7 +++++++
 arch/riscv/dts/erizo.dtsi         |  2 ++
 arch/riscv/include/asm/timer.h    |  1 +
 drivers/clocksource/timer-riscv.c | 19 ++++++++-----------
 4 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/arch/riscv/cpu/time.c b/arch/riscv/cpu/time.c
index 39bb6a5112..59c8ca61d6 100644
--- a/arch/riscv/cpu/time.c
+++ b/arch/riscv/cpu/time.c
@@ -18,6 +18,7 @@
 #include <asm/timer.h>
 
 unsigned long riscv_timebase;
+unsigned long riscv_use_csr_cycle;
 
 int timer_init(void)
 {
@@ -32,6 +33,12 @@ int timer_init(void)
 
 	riscv_timebase = prop;
 
+	if (of_property_read_bool(cpu, "csr-cycle")) {
+		riscv_use_csr_cycle = 1;
+	} else {
+		riscv_use_csr_cycle = 0;
+	}
+
 	of_platform_populate(cpu, NULL, NULL);
 
 	return 0;
diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi
index 228711bd69..b3ccf281f2 100644
--- a/arch/riscv/dts/erizo.dtsi
+++ b/arch/riscv/dts/erizo.dtsi
@@ -22,6 +22,8 @@
 
 		timebase-frequency = <24000000>;
 
+		csr-cycle;
+
 		cpu@0 {
 			device_type = "cpu";
 			compatible = "cliffordwolf,picorv32", "riscv";
diff --git a/arch/riscv/include/asm/timer.h b/arch/riscv/include/asm/timer.h
index 1f78ef4c00..555b3f5989 100644
--- a/arch/riscv/include/asm/timer.h
+++ b/arch/riscv/include/asm/timer.h
@@ -5,5 +5,6 @@
 
 int timer_init(void);
 extern unsigned long riscv_timebase;
+extern unsigned long riscv_use_csr_cycle;
 
 #endif /* _ASM_RISCV_DELAY_H */
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index ef67cff475..c0deed40eb 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -13,7 +13,7 @@
 #include <asm/timer.h>
 #include <asm/csr.h>
 
-static u64 notrace riscv_timer_get_count_sbi(void)
+static u64 notrace riscv_timer_get_count_time(void)
 {
 	__maybe_unused u32 hi, lo;
 
@@ -28,7 +28,7 @@ static u64 notrace riscv_timer_get_count_sbi(void)
 	return ((u64)hi << 32) | lo;
 }
 
-static u64 notrace riscv_timer_get_count_rdcycle(void)
+static u64 notrace riscv_timer_get_count_cycle(void)
 {
 	__maybe_unused u32 hi, lo;
 
@@ -43,16 +43,7 @@ static u64 notrace riscv_timer_get_count_rdcycle(void)
 	return ((u64)hi << 32) | lo;
 }
 
-static u64 notrace riscv_timer_get_count(void)
-{
-	if (IS_ENABLED(CONFIG_RISCV_SBI))
-		return riscv_timer_get_count_sbi();
-	else
-		return riscv_timer_get_count_rdcycle();
-}
-
 static struct clocksource riscv_clocksource = {
-	.read		= riscv_timer_get_count,
 	.mask		= CLOCKSOURCE_MASK(64),
 	.priority	= 100,
 };
@@ -61,6 +52,12 @@ static int riscv_timer_init(struct device_d* dev)
 {
 	dev_info(dev, "running at %lu Hz\n", riscv_timebase);
 
+	if (riscv_use_csr_cycle) {
+		riscv_clocksource.read = riscv_timer_get_count_cycle;
+	} else {
+		riscv_clocksource.read = riscv_timer_get_count_time;
+	}
+
 	riscv_clocksource.mult = clocksource_hz2mult(riscv_timebase, riscv_clocksource.shift);
 
 	return init_clock(&riscv_clocksource);
-- 
2.31.1


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  reply	other threads:[~2021-05-06 22:10 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-06 22:08 [PATCH v2 00/11] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
2021-05-06 22:08 ` Antony Pavlov [this message]
2021-05-07 11:34   ` [PATCH v2 01/11] clocksource: timer-riscv: select CSR from device tree Ahmad Fatoum
2021-05-07 17:41     ` Antony Pavlov
2021-05-07 18:05       ` Ahmad Fatoum
2021-05-06 22:08 ` [PATCH v2 02/11] RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive Antony Pavlov
2021-05-07 11:42   ` Ahmad Fatoum
2021-05-07 14:25     ` Antony Pavlov
2021-05-07 14:44       ` Ahmad Fatoum
2021-05-07 17:52         ` Antony Pavlov
2021-05-07 18:08           ` Ahmad Fatoum
2021-05-07 18:36             ` Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 03/11] RISC-V: make it possible to run nmon from PBL C code Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 04/11] RISC-V: boards: erizo: make it possible to use nmon Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 05/11] serial: add litex UART driver Antony Pavlov
2021-05-07 11:45   ` Ahmad Fatoum
2021-05-07 12:02     ` Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 06/11] gpio: add driver for 74xx-ICs with MMIO access Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 07/11] spi: add litex spiflash driver Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 08/11] net: add LiteEth driver Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 09/11] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 10/11] RISC-V: add litex_linux_defconfig Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 11/11] RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n Antony Pavlov
2021-05-07 10:27   ` Ahmad Fatoum
2021-05-07 10:23 ` [PATCH v2 00/11] RISC-V: add LiteX SoC support; resurrect nmon Ahmad Fatoum
2021-05-07 11:12   ` Antony Pavlov

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