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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Antony Pavlov <antonynpavlov@gmail.com>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH v2 02/11] RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive
Date: Fri, 7 May 2021 16:44:24 +0200	[thread overview]
Message-ID: <28074d89-492c-48ac-d93e-103092e073cd@pengutronix.de> (raw)
In-Reply-To: <20210507172527.cf80cf7cb749560d2e8200cd@gmail.com>

Hello Antony,

On 07.05.21 16:25, Antony Pavlov wrote:
>> I would really like to have a riscv{32,64}_defconfig that can just build all boards
>> at once. Do you know if this could be dynamically determined?
> 
> At the moment I have not answer.
> I'll try to investigate dynamic mode determination, it's very attractive idea.
> 
> On the other hand compile time mode selection is not the show stopper for
> "one defconfig to build them all": we have to make STACK_SIZE and MALLOC_SIZE
> per-board parameters not per-defconfig parameters like now.
> 
> If we could make STACK_SIZE and MALLOC_SIZE per-board compile-time parameters then
> we can make RISC-V mode per-board compile-time parameter too. Is this solution
> acceptable?

MALLOC_SIZE can be set as 0 and barebox will determine it based on
membase + memsize that are set by PBL.

STACK_SIZE must be set per Kconfig, but I think even a generous default stack
size should accommodate all targets.

If we do the same for RISC-V mode that would probably mean having
two functions barebox_riscv_machine_entry() and barebox_riscv_supervisor_entry()
in PBL that take care to pass the correct info to barebox proper.

Apparently, you can determine mode if you catch exceptions:
https://forums.sifive.com/t/how-to-determine-the-current-execution-privilege-mode/2823

We don't yet install exception handlers in barebox, but I am fine with using
different PBL common code entry functions.

What do you think?

Cheers,
Ahmad

> 
>>> +
>>>  source "arch/riscv/Kconfig.socs"
>>>  
>>>  config CPU_SUPPORTS_32BIT_KERNEL
>>> @@ -97,14 +109,4 @@ config NMON_HELP
>>>  	  Say yes here to get the nmon commands message on
>>>  	  every nmon start.
>>>  
>>> -# set if we run in machine mode, cleared if we run in supervisor mode
>>> -config RISCV_M_MODE
>>> -	bool
>>> -
>>> -# set if we are running in S-mode and can use SBI calls
>>> -config RISCV_SBI
>>> -	bool
>>> -	depends on !RISCV_M_MODE
>>> -	default y
>>> -
>>>  endmenu
>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>>> index c6875738d0..f767942f34 100644
>>> --- a/arch/riscv/Kconfig.socs
>>> +++ b/arch/riscv/Kconfig.socs
>>> @@ -3,10 +3,10 @@ menu "SoC selection"
>>>  config SOC_ERIZO
>>>  	bool "Erizo SoC"
>>>  	depends on ARCH_RV32I
>>> +	depends on RISCV_M_MODE
>>>  	select HAS_ASM_DEBUG_LL
>>>  	select HAS_NMON
>>>  	select USE_COMPRESSED_DTB
>>> -	select RISCV_M_MODE
>>>  	select RISCV_TIMER
>>>  
>>>  config BOARD_ERIZO_GENERIC
>>> @@ -15,6 +15,7 @@ config BOARD_ERIZO_GENERIC
>>>  
>>>  config SOC_VIRT
>>>  	bool "QEMU Virt Machine"
>>> +	depends on RISCV_SBI
>>>  	select BOARD_RISCV_GENERIC_DT
>>>  	select CLINT_TIMER
>>>  	help
>>> @@ -23,6 +24,7 @@ config SOC_VIRT
>>>  
>>>  config SOC_SIFIVE
>>>  	bool "SiFive SoCs"
>>> +	depends on RISCV_SBI
>>>  	select CLK_SIFIVE
>>>  	select CLK_SIFIVE_PRCI
>>>  	select RISCV_TIMER
>>> diff --git a/arch/riscv/configs/erizo_generic_defconfig b/arch/riscv/configs/erizo_generic_defconfig
>>> index 247a179130..16168eef66 100644
>>> --- a/arch/riscv/configs/erizo_generic_defconfig
>>> +++ b/arch/riscv/configs/erizo_generic_defconfig
>>> @@ -1,3 +1,4 @@
>>> +CONFIG_RISCV_M_MODE=y
>>>  CONFIG_SOC_ERIZO=y
>>>  # CONFIG_GLOBALVAR is not set
>>>  CONFIG_STACK_SIZE=0x20000
>>>
>>
>> -- 
>> Pengutronix e.K.                           |                             |
>> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
>> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
>> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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  reply	other threads:[~2021-05-07 14:45 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-06 22:08 [PATCH v2 00/11] RISC-V: add LiteX SoC support; resurrect nmon Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 01/11] clocksource: timer-riscv: select CSR from device tree Antony Pavlov
2021-05-07 11:34   ` Ahmad Fatoum
2021-05-07 17:41     ` Antony Pavlov
2021-05-07 18:05       ` Ahmad Fatoum
2021-05-06 22:08 ` [PATCH v2 02/11] RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive Antony Pavlov
2021-05-07 11:42   ` Ahmad Fatoum
2021-05-07 14:25     ` Antony Pavlov
2021-05-07 14:44       ` Ahmad Fatoum [this message]
2021-05-07 17:52         ` Antony Pavlov
2021-05-07 18:08           ` Ahmad Fatoum
2021-05-07 18:36             ` Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 03/11] RISC-V: make it possible to run nmon from PBL C code Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 04/11] RISC-V: boards: erizo: make it possible to use nmon Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 05/11] serial: add litex UART driver Antony Pavlov
2021-05-07 11:45   ` Ahmad Fatoum
2021-05-07 12:02     ` Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 06/11] gpio: add driver for 74xx-ICs with MMIO access Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 07/11] spi: add litex spiflash driver Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 08/11] net: add LiteEth driver Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 09/11] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 10/11] RISC-V: add litex_linux_defconfig Antony Pavlov
2021-05-06 22:08 ` [PATCH v2 11/11] RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n Antony Pavlov
2021-05-07 10:27   ` Ahmad Fatoum
2021-05-07 10:23 ` [PATCH v2 00/11] RISC-V: add LiteX SoC support; resurrect nmon Ahmad Fatoum
2021-05-07 11:12   ` Antony Pavlov

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