From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Renaud Barbier <renaud.barbier@abaco.com>, barebox@lists.infradead.org
Subject: Re: [PATCH 3/4] nand: add NXP IFC nand driver
Date: Thu, 29 Jul 2021 12:11:54 +0200 [thread overview]
Message-ID: <2b7ebb39-c70a-b02e-767d-cedb90494d7a@pengutronix.de> (raw)
In-Reply-To: <1627476428-16318-4-git-send-email-renaud.barbier@abaco.com>
On 28.07.21 14:47, Renaud Barbier wrote:
> Add the NXP IFC nand driver support. This driver
> can be used with the NXP QorIQ cores.
>
> Signed-off-by: Renaud Barbier <renaud.barbier@abaco.com>
> ---
> .../mach-layerscape/include/mach/fsl_ifc.h | 16 +
> .../mach-layerscape/include/mach/layerscape.h | 3 +
> drivers/mtd/nand/Kconfig | 6 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/fsl_ifc.h | 116 ++
> drivers/mtd/nand/nand_fsl_ifc.c | 1037 +++++++++++++++++
> include/linux/fsl_ifc.h | 306 +++++
> 7 files changed, 1485 insertions(+)
> create mode 100644 arch/arm/mach-layerscape/include/mach/fsl_ifc.h
> create mode 100644 drivers/mtd/nand/fsl_ifc.h
> create mode 100644 drivers/mtd/nand/nand_fsl_ifc.c
> create mode 100644 include/linux/fsl_ifc.h
>
> diff --git a/arch/arm/mach-layerscape/include/mach/fsl_ifc.h b/arch/arm/mach-layerscape/include/mach/fsl_ifc.h
> new file mode 100644
> index 0000000000..385d07cb1f
> --- /dev/null
> +++ b/arch/arm/mach-layerscape/include/mach/fsl_ifc.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2021 Abaco Systems, Inc
> + */
> +
> +#ifndef __MACH_MTD_FSL_IFC
> +#define __MACH_MTD_FSL_IFC
> +
> +#include <mach/layerscape.h>
> +#include <linux/fsl_ifc.h>
> +
> +
> +struct fsl_ifc_data {
> + uint32_t cs;
> +};
> +#endif
Header can be dropped as the Layerscape support is DT-only.
> diff --git a/arch/arm/mach-layerscape/include/mach/layerscape.h b/arch/arm/mach-layerscape/include/mach/layerscape.h
> index 1f1da0f66e..cb7bbc56b0 100644
> --- a/arch/arm/mach-layerscape/include/mach/layerscape.h
> +++ b/arch/arm/mach-layerscape/include/mach/layerscape.h
> @@ -3,6 +3,9 @@
>
> #define LS1046A_DDR_SDRAM_BASE 0x80000000
> #define LS1046A_DDR_FREQ 2100000000
> +#define LS10146A_IFC_ADDR 0x01530000
> +
> +#define IFC_ADDR LS10146A_IFC_ADDR
That's a too generic macro name. You should retrieve the base address
from device tree in the driver. Otherwise, if a new Layerscape SoC
is added, you won't be able to have a multi-image barebox build
that supports both.
> +static int fsl_ifc_nand_probe(struct device_d *dev)
> +{
> + struct device_node *np = dev->device_node;
> + struct fsl_ifc_data *pdata = dev->platform_data;
> + struct fsl_ifc_mtd *priv;
> + struct resource *iores;
> + struct mtd_info *mtd;
> + int ret = 0;
> +
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->dev = dev;
> + if (!np) {
I'd remove the PPC non-DT support. It doesn't compile now anyway.
Cheers,
Ahmad
--
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next prev parent reply other threads:[~2021-07-29 10:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-28 12:47 [PATCH 0/4] " Renaud Barbier
2021-07-28 12:47 ` [PATCH 1/4] ARM: atomic.h: add 64-bit counter support Renaud Barbier
2021-07-29 9:58 ` Ahmad Fatoum
2021-07-28 12:47 ` [PATCH 2/4] arm: 64-bit device specific operation Renaud Barbier
2021-07-29 10:00 ` Ahmad Fatoum
2021-07-28 12:47 ` [PATCH 3/4] nand: add NXP IFC nand driver Renaud Barbier
2021-07-29 10:11 ` Ahmad Fatoum [this message]
2021-07-28 12:47 ` [PATCH 4/4] ls1046ardb: enable IFC NAND Renaud Barbier
2021-07-29 10:13 ` Ahmad Fatoum
2021-07-29 18:19 ` Barbier, Renaud
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