* [PATCH 1/3] arm: socfpga: replace custom UART with ns16550
2026-06-05 12:58 [PATCH 0/3] arm: socfpga: cleanup UART for serial console Michael Tretter
@ 2026-06-05 12:58 ` Michael Tretter
2026-06-05 12:58 ` [PATCH 2/3] arm: socfpga: get rid of UART address for low-level debug Michael Tretter
2026-06-05 12:58 ` [PATCH 3/3] arm: socfpga: axe5-eagle: always use UART0 Michael Tretter
2 siblings, 0 replies; 4+ messages in thread
From: Michael Tretter @ 2026-06-05 12:58 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: Michael Tretter
There is nothing special in the SoCFPGA UART, but it is compatible with
an ns16550 uart. Remove the custom implementation.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
include/mach/socfpga/debug_ll.h | 104 ++++++++++++++--------------------------
1 file changed, 35 insertions(+), 69 deletions(-)
diff --git a/include/mach/socfpga/debug_ll.h b/include/mach/socfpga/debug_ll.h
index 698cca60373f..86f6256af995 100644
--- a/include/mach/socfpga/debug_ll.h
+++ b/include/mach/socfpga/debug_ll.h
@@ -4,97 +4,63 @@
#define __MACH_SOCFPGA_DEBUG_LL_H__
#include <io.h>
-#include <errno.h>
#ifdef CONFIG_DEBUG_LL
#define UART_BASE CONFIG_DEBUG_SOCFPGA_UART_PHYS_ADDR
+
+#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
+static inline uint8_t debug_ll_read_reg(void __iomem *base, int reg)
+{
+ return readb(base + (reg << 2));
+}
+
+static inline void debug_ll_write_reg(void __iomem *base, int reg, uint8_t val)
+{
+ writeb(val, base + (reg << 2));
+}
+#else
+static inline uint8_t debug_ll_read_reg(void __iomem *base, int reg)
+{
+ return readl(base + (reg << 2));
+}
+
+static inline void debug_ll_write_reg(void __iomem *base, int reg, uint8_t val)
+{
+ writel(val, base + (reg << 2));
+}
#endif
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-#define LSR_TEMT 0x40
+#include <debug_ll/ns16550.h>
-#define LCR_BKSE 0x80 /* Bank select enable */
-#define LCRVAL 0x3
-#define MCRVAL 0x3
-#define FCRVAL 0xc1
-
-#define RBR 0x0
-#define DLL 0x0
-#define IER 0x4
-#define DLM 0x4
-#define FCR 0x8
-#define LCR 0xc
-#define MCR 0x10
-#define LSR 0x14
-#define MSR 0x18
-#define SCR 0x1c
-#define THR 0x30
-
-static inline void socfpga_gen5_uart_putc(void *base, int c)
+static inline void socfpga_uart_setup(void *base)
{
- /* Wait until there is space in the FIFO */
- while ((readb(base + LSR) & LSR_THRE) == 0);
- /* Send the character */
- writeb(c, base + THR);
- /* Wait to make sure it hits the line, in case we die too soon. */
- while ((readb(base + LSR) & LSR_THRE) == 0);
-}
+ unsigned int div;
-static inline void socfpga_uart_putc(void *base, int c)
-{
- /* Wait until there is space in the FIFO */
- while ((readl(base + LSR) & LSR_THRE) == 0);
- /* Send the character */
- writel(c, base + THR);
- /* Wait to make sure it hits the line, in case we die too soon. */
- while ((readl(base + LSR) & LSR_THRE) == 0);
-}
-
-#ifdef CONFIG_DEBUG_LL
-static inline unsigned int ns16550_calc_divisor(unsigned int clk,
- unsigned int baudrate)
-{
- return (clk / 16 / baudrate);
+ div = debug_ll_ns16550_calc_divisor(CONFIG_DEBUG_SOCFPGA_UART_CLOCK);
+ debug_ll_ns16550_init(base, div);
}
static inline void socfpga_uart_setup_ll(void)
-{
- unsigned int div = ns16550_calc_divisor(CONFIG_DEBUG_SOCFPGA_UART_CLOCK,
- 115200);
-
- writel(0x00, UART_BASE + IER);
-
- writel(LCR_BKSE, UART_BASE + LCR);
- writel(div & 0xff, UART_BASE + DLL);
- writel((div >> 8) & 0xff, UART_BASE + DLM);
- writel(LCRVAL, UART_BASE + LCR);
-
- writel(MCRVAL, UART_BASE + MCR);
- writel(FCRVAL, UART_BASE + FCR);
-}
-
-#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
-static inline void PUTC_LL(char c)
{
void __iomem *base = IOMEM(UART_BASE);
- socfpga_gen5_uart_putc(base, c);
+ socfpga_uart_setup(base);
}
-#else
+
+static inline void socfpga_uart_putc(void *base, int c)
+{
+ debug_ll_ns16550_putc(base, c);
+}
+
static inline void PUTC_LL(char c)
{
void __iomem *base = IOMEM(UART_BASE);
socfpga_uart_putc(base, c);
}
-#endif
-
#else
-static inline unsigned int ns16550_calc_divisor(unsigned int clk,
- unsigned int baudrate) {
- return -ENOSYS;
-}
static inline void socfpga_uart_setup_ll(void) {}
-static inline void PUTC_LL(char c) {}
+static inline void socfpga_uart_putc(void *base, int c) {}
+static inline void socfpga_uart_setup(void *base) {}
#endif
#endif /* __MACH_SOCFPGA_DEBUG_LL_H__ */
--
2.47.3
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH 2/3] arm: socfpga: get rid of UART address for low-level debug
2026-06-05 12:58 [PATCH 0/3] arm: socfpga: cleanup UART for serial console Michael Tretter
2026-06-05 12:58 ` [PATCH 1/3] arm: socfpga: replace custom UART with ns16550 Michael Tretter
@ 2026-06-05 12:58 ` Michael Tretter
2026-06-05 12:58 ` [PATCH 3/3] arm: socfpga: axe5-eagle: always use UART0 Michael Tretter
2 siblings, 0 replies; 4+ messages in thread
From: Michael Tretter @ 2026-06-05 12:58 UTC (permalink / raw)
To: Sascha Hauer, BAREBOX; +Cc: Michael Tretter
There are existing address definitions for UART0 and UART1 on SoCFPGA.
Having the UART address in the config is error prone.
Change it to debug ports, which allow to select the UART instead of
setting the address. While at it, simplify the configuration.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
common/Kconfig.debug_ll | 44 +++++++++++------------------------------
include/mach/socfpga/debug_ll.h | 9 +++++++--
2 files changed, 18 insertions(+), 35 deletions(-)
diff --git a/common/Kconfig.debug_ll b/common/Kconfig.debug_ll
index 3f06e2eef418..650bfe56383e 100644
--- a/common/Kconfig.debug_ll
+++ b/common/Kconfig.debug_ll
@@ -238,33 +238,12 @@ config DEBUG_ROCKCHIP_RK3399_UART
Say Y here if you want kernel low-level debugging support
on RK3399.
-config DEBUG_SOCFPGA_UART0
- bool "Use SOCFPGA UART0 for low-level debug"
+config DEBUG_SOCFPGA_UART
+ bool "SoCFPGA Debug UART"
depends on ARCH_SOCFPGA
help
Say Y here if you want kernel low-level debugging support
- on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
-
-config DEBUG_SOCFPGA_UART1
- bool "Use SOCFPGA UART1 for low-level debug"
- depends on ARCH_SOCFPGA
- help
- Say Y here if you want kernel low-level debugging support
- on SOCFPGA(Arria 10) based platforms.
-
-config DEBUG_SOCFPGA_AGILEX5_UART0
- bool "Use Agilex5 UART0 for low-level debug"
- depends on ARCH_SOCFPGA_AGILEX5
- help
- Say Y here if you want kernel low-level debugging support
- on Agilex5 based platforms.
-
-config DEBUG_SOCFPGA_AGILEX5_UART1
- bool "Use Agilex5 UART1 for low-level debug"
- depends on ARCH_SOCFPGA_AGILEX5
- help
- Say Y here if you want kernel low-level debugging support
- on Agilex5 based platforms.
+ on SoCFPGA based platforms.
config DEBUG_STM32MP_UART
bool "Use STM32MP UART4 for low-level debug"
@@ -482,19 +461,18 @@ config DEBUG_ROCKCHIP_UART_PORT
Choose UART port on which kernel low-level debug messages
should be output.
-config DEBUG_SOCFPGA_UART_PHYS_ADDR
- hex "Physical base address of debug UART" if DEBUG_LL
- default 0xffc02000 if DEBUG_SOCFPGA_UART0
- default 0xffc02100 if DEBUG_SOCFPGA_UART1
- default 0x10c02000 if DEBUG_SOCFPGA_AGILEX5_UART0
- default 0x10c02100 if DEBUG_SOCFPGA_AGILEX5_UART1
+config DEBUG_SOCFPGA_UART_PORT
+ int "SocFPGA UART debug port" if DEBUG_SOCFPGA_UART
+ default 0 if ARCH_SOCFPGA_CYCLONE5 || ARCH_SOCFPGA_AGILEX5
+ default 1 if ARCH_SOCFPGA_ARRIA10
depends on ARCH_SOCFPGA
+ help
+ Select UART port used for early debugging.
config DEBUG_SOCFPGA_UART_CLOCK
- int "SoCFPGA UART debug clock" if DEBUG_LL
- default 100000000 if ARCH_SOCFPGA_CYCLONE5
+ int "SoCFPGA UART debug clock" if DEBUG_SOCFPGA_UART
+ default 100000000 if ARCH_SOCFPGA_CYCLONE5 || ARCH_SOCFPGA_AGILEX5
default 50000000 if ARCH_SOCFPGA_ARRIA10
- default 100000000 if ARCH_SOCFPGA_AGILEX5
depends on ARCH_SOCFPGA
help
Choose UART root clock.
diff --git a/include/mach/socfpga/debug_ll.h b/include/mach/socfpga/debug_ll.h
index 86f6256af995..3d69d87545c1 100644
--- a/include/mach/socfpga/debug_ll.h
+++ b/include/mach/socfpga/debug_ll.h
@@ -4,9 +4,14 @@
#define __MACH_SOCFPGA_DEBUG_LL_H__
#include <io.h>
+#include <mach/socfpga/soc64-regs.h>
-#ifdef CONFIG_DEBUG_LL
-#define UART_BASE CONFIG_DEBUG_SOCFPGA_UART_PHYS_ADDR
+#define __SOCFPGA_UART_BASE(num) SOCFPGA_UART##num##_ADDRESS
+#define SOCFPGA_UART_BASE(num) __SOCFPGA_UART_BASE(num)
+
+#ifdef CONFIG_DEBUG_SOCFPGA_UART
+
+#define UART_BASE SOCFPGA_UART_BASE(CONFIG_DEBUG_SOCFPGA_UART_PORT)
#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
static inline uint8_t debug_ll_read_reg(void __iomem *base, int reg)
--
2.47.3
^ permalink raw reply [flat|nested] 4+ messages in thread