[PATCH 0/3] arm: socfpga: cleanup UART for serial console

[PATCH 0/3] arm: socfpga: cleanup UART for serial console

[Michael Tretter]

Configuring debug console output for the PBL and low level code on
SoCFPGA boards is surprisingly complex and an inconsistent configuration
bit me more than once.

Get rid of the custom UART implementation and the base addresses for the
debug UART in the barebox configuration.

While at it, set the debug UART for the Arrow AXE5 board in the board
code and don't force the developer to know and configure the correct
debug UART in the configuration.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
Michael Tretter (3):
      arm: socfpga: replace custom UART with ns16550
      arm: socfpga: get rid of UART address for low-level debug
      arm: socfpga: axe5-eagle: always use UART0

 arch/arm/boards/arrow-axe5-eagle/lowlevel.c |   6 +-
 common/Kconfig.debug_ll                     |  44 +++--------
 include/mach/socfpga/debug_ll.h             | 113 +++++++++++-----------------
 3 files changed, 57 insertions(+), 106 deletions(-)
---
base-commit: 713a1e59dfea4516446822323b7c0db571cb214f
change-id: 20260605-socfpga-debug-uart-d840aa594751

Best regards,
-- 
Michael Tretter <m.tretter@pengutronix.de>

[PATCH 1/3] arm: socfpga: replace custom UART with ns16550

[Michael Tretter]

There is nothing special in the SoCFPGA UART, but it is compatible with
an ns16550 uart. Remove the custom implementation.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 include/mach/socfpga/debug_ll.h | 104 ++++++++++++++--------------------------
 1 file changed, 35 insertions(+), 69 deletions(-)

diff --git a/include/mach/socfpga/debug_ll.h b/include/mach/socfpga/debug_ll.h
index 698cca60373f..86f6256af995 100644
--- a/include/mach/socfpga/debug_ll.h
+++ b/include/mach/socfpga/debug_ll.h
@@ -4,97 +4,63 @@
 #define   __MACH_SOCFPGA_DEBUG_LL_H__
 
 #include <io.h>
-#include <errno.h>
 
 #ifdef CONFIG_DEBUG_LL
 #define UART_BASE	CONFIG_DEBUG_SOCFPGA_UART_PHYS_ADDR
+
+#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
+static inline uint8_t debug_ll_read_reg(void __iomem *base, int reg)
+{
+	return readb(base + (reg << 2));
+}
+
+static inline void debug_ll_write_reg(void __iomem *base, int reg, uint8_t val)
+{
+	writeb(val, base + (reg << 2));
+}
+#else
+static inline uint8_t debug_ll_read_reg(void __iomem *base, int reg)
+{
+	return readl(base + (reg << 2));
+}
+
+static inline void debug_ll_write_reg(void __iomem *base, int reg, uint8_t val)
+{
+	writel(val, base + (reg << 2));
+}
 #endif
 
-#define LSR_THRE	0x20	/* Xmit holding register empty */
-#define LSR_TEMT	0x40
+#include <debug_ll/ns16550.h>
 
-#define LCR_BKSE	0x80	/* Bank select enable */
-#define LCRVAL		0x3
-#define MCRVAL		0x3
-#define FCRVAL		0xc1
-
-#define RBR		0x0
-#define DLL		0x0
-#define IER		0x4
-#define DLM		0x4
-#define FCR		0x8
-#define LCR		0xc
-#define MCR		0x10
-#define LSR		0x14
-#define MSR		0x18
-#define SCR		0x1c
-#define THR		0x30
-
-static inline void socfpga_gen5_uart_putc(void *base, int c)
+static inline void socfpga_uart_setup(void *base)
 {
-	/* Wait until there is space in the FIFO */
-	while ((readb(base + LSR) & LSR_THRE) == 0);
-	/* Send the character */
-	writeb(c, base + THR);
-	/* Wait to make sure it hits the line, in case we die too soon. */
-	while ((readb(base + LSR) & LSR_THRE) == 0);
-}
+	unsigned int div;
 
-static inline void socfpga_uart_putc(void *base, int c)
-{
-	/* Wait until there is space in the FIFO */
-	while ((readl(base + LSR) & LSR_THRE) == 0);
-	/* Send the character */
-	writel(c, base + THR);
-	/* Wait to make sure it hits the line, in case we die too soon. */
-	while ((readl(base + LSR) & LSR_THRE) == 0);
-}
-
-#ifdef CONFIG_DEBUG_LL
-static inline unsigned int ns16550_calc_divisor(unsigned int clk,
-					 unsigned int baudrate)
-{
-	return (clk / 16 / baudrate);
+	div = debug_ll_ns16550_calc_divisor(CONFIG_DEBUG_SOCFPGA_UART_CLOCK);
+	debug_ll_ns16550_init(base, div);
 }
 
 static inline void socfpga_uart_setup_ll(void)
-{
-	unsigned int div = ns16550_calc_divisor(CONFIG_DEBUG_SOCFPGA_UART_CLOCK,
-						115200);
-
-	writel(0x00, UART_BASE + IER);
-
-	writel(LCR_BKSE, UART_BASE + LCR);
-	writel(div & 0xff, UART_BASE + DLL);
-	writel((div >> 8) & 0xff, UART_BASE + DLM);
-	writel(LCRVAL, UART_BASE + LCR);
-
-	writel(MCRVAL, UART_BASE + MCR);
-	writel(FCRVAL, UART_BASE + FCR);
-}
-
-#if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
-static inline void PUTC_LL(char c)
 {
 	void __iomem *base = IOMEM(UART_BASE);
 
-	socfpga_gen5_uart_putc(base, c);
+	socfpga_uart_setup(base);
 }
-#else
+
+static inline void socfpga_uart_putc(void *base, int c)
+{
+	debug_ll_ns16550_putc(base, c);
+}
+
 static inline void PUTC_LL(char c)
 {
 	void __iomem *base = IOMEM(UART_BASE);
 
 	socfpga_uart_putc(base, c);
 }
-#endif
-
 #else
-static inline unsigned int ns16550_calc_divisor(unsigned int clk,
-					 unsigned int baudrate) {
-	return -ENOSYS;
-}
 static inline void socfpga_uart_setup_ll(void) {}
-static inline void PUTC_LL(char c) {}
+static inline void socfpga_uart_putc(void *base, int c) {}
+static inline void socfpga_uart_setup(void *base) {}
 #endif
 #endif /* __MACH_SOCFPGA_DEBUG_LL_H__ */

-- 
2.47.3

[PATCH 2/3] arm: socfpga: get rid of UART address for low-level debug

[Michael Tretter]

There are existing address definitions for UART0 and UART1 on SoCFPGA.
Having the UART address in the config is error prone.

Change it to debug ports, which allow to select the UART instead of
setting the address. While at it, simplify the configuration.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 common/Kconfig.debug_ll         | 44 +++++++++++------------------------------
 include/mach/socfpga/debug_ll.h |  9 +++++++--
 2 files changed, 18 insertions(+), 35 deletions(-)

diff --git a/common/Kconfig.debug_ll b/common/Kconfig.debug_ll
index 3f06e2eef418..650bfe56383e 100644
--- a/common/Kconfig.debug_ll
+++ b/common/Kconfig.debug_ll
@@ -238,33 +238,12 @@ config DEBUG_ROCKCHIP_RK3399_UART
 	  Say Y here if you want kernel low-level debugging support
 	  on RK3399.
 
-config DEBUG_SOCFPGA_UART0
-	bool "Use SOCFPGA UART0 for low-level debug"
+config DEBUG_SOCFPGA_UART
+	bool "SoCFPGA Debug UART"
 	depends on ARCH_SOCFPGA
 	help
 	  Say Y here if you want kernel low-level debugging support
-	  on SOCFPGA(Cyclone 5 and Arria 5) based platforms.
-
-config DEBUG_SOCFPGA_UART1
-	bool "Use SOCFPGA UART1 for low-level debug"
-	depends on ARCH_SOCFPGA
-	help
-	  Say Y here if you want kernel low-level debugging support
-	  on SOCFPGA(Arria 10) based platforms.
-
-config DEBUG_SOCFPGA_AGILEX5_UART0
-	bool "Use Agilex5 UART0 for low-level debug"
-	depends on ARCH_SOCFPGA_AGILEX5
-	help
-	  Say Y here if you want kernel low-level debugging support
-	  on Agilex5 based platforms.
-
-config DEBUG_SOCFPGA_AGILEX5_UART1
-	bool "Use Agilex5 UART1 for low-level debug"
-	depends on ARCH_SOCFPGA_AGILEX5
-	help
-	  Say Y here if you want kernel low-level debugging support
-	  on Agilex5 based platforms.
+	  on SoCFPGA based platforms.
 
 config DEBUG_STM32MP_UART
 	bool "Use STM32MP UART4 for low-level debug"
@@ -482,19 +461,18 @@ config DEBUG_ROCKCHIP_UART_PORT
 	  Choose UART port on which kernel low-level debug messages
 	  should be output.
 
-config DEBUG_SOCFPGA_UART_PHYS_ADDR
-	hex "Physical base address of debug UART" if DEBUG_LL
-	default 0xffc02000 if DEBUG_SOCFPGA_UART0
-	default 0xffc02100 if DEBUG_SOCFPGA_UART1
-	default 0x10c02000 if DEBUG_SOCFPGA_AGILEX5_UART0
-	default 0x10c02100 if DEBUG_SOCFPGA_AGILEX5_UART1
+config DEBUG_SOCFPGA_UART_PORT
+	int "SocFPGA UART debug port" if DEBUG_SOCFPGA_UART
+	default 0 if ARCH_SOCFPGA_CYCLONE5 || ARCH_SOCFPGA_AGILEX5
+	default 1 if ARCH_SOCFPGA_ARRIA10
 	depends on ARCH_SOCFPGA
+	help
+	  Select UART port used for early debugging.
 
 config DEBUG_SOCFPGA_UART_CLOCK
-	int "SoCFPGA UART debug clock" if DEBUG_LL
-	default 100000000 if ARCH_SOCFPGA_CYCLONE5
+	int "SoCFPGA UART debug clock" if DEBUG_SOCFPGA_UART
+	default 100000000 if ARCH_SOCFPGA_CYCLONE5 || ARCH_SOCFPGA_AGILEX5
 	default  50000000 if ARCH_SOCFPGA_ARRIA10
-	default 100000000 if ARCH_SOCFPGA_AGILEX5
 	depends on ARCH_SOCFPGA
 	help
 	  Choose UART root clock.
diff --git a/include/mach/socfpga/debug_ll.h b/include/mach/socfpga/debug_ll.h
index 86f6256af995..3d69d87545c1 100644
--- a/include/mach/socfpga/debug_ll.h
+++ b/include/mach/socfpga/debug_ll.h
@@ -4,9 +4,14 @@
 #define   __MACH_SOCFPGA_DEBUG_LL_H__
 
 #include <io.h>
+#include <mach/socfpga/soc64-regs.h>
 
-#ifdef CONFIG_DEBUG_LL
-#define UART_BASE	CONFIG_DEBUG_SOCFPGA_UART_PHYS_ADDR
+#define __SOCFPGA_UART_BASE(num)	SOCFPGA_UART##num##_ADDRESS
+#define SOCFPGA_UART_BASE(num)		__SOCFPGA_UART_BASE(num)
+
+#ifdef CONFIG_DEBUG_SOCFPGA_UART
+
+#define UART_BASE			SOCFPGA_UART_BASE(CONFIG_DEBUG_SOCFPGA_UART_PORT)
 
 #if defined(CONFIG_ARCH_SOCFPGA_CYCLONE5)
 static inline uint8_t debug_ll_read_reg(void __iomem *base, int reg)

-- 
2.47.3

[PATCH 3/3] arm: socfpga: axe5-eagle: always use UART0

[Michael Tretter]

Configuring debug_ll with the UART from the configuration, while
configuring the PBL console with a hard-coded address may lead to
inconsistencies and confusion.

Avoid this by explicitly configuring debug_ll with a UART defined by the
board low level code.

While at it, replace the address with the UART port macro.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/boards/arrow-axe5-eagle/lowlevel.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
index f946a8b9f616..b0a2d6673e0f 100644
--- a/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
+++ b/arch/arm/boards/arrow-axe5-eagle/lowlevel.c
@@ -15,10 +15,12 @@ extern char __dtb_z_socfpga_agilex5_axe5_eagle_start[];
 
 static noinline void axe5_eagle_continue(void)
 {
+	void __iomem *uart = IOMEM(SOCFPGA_UART_BASE(0));
+
 	agilex5_clk_init();
 
-	socfpga_uart_setup_ll();
-	pbl_set_putc(socfpga_uart_putc, (void *) SOCFPGA_UART0_ADDRESS);
+	socfpga_uart_setup(uart);
+	pbl_set_putc(socfpga_uart_putc, uart);
 
 	pr_debug("Lowlevel init done\n");
 

-- 
2.47.3