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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH v2 28/29] misc: add power sequencing driver for initializing StarFive peripherals
Date: Sat, 19 Jun 2021 06:50:54 +0200	[thread overview]
Message-ID: <20210619045055.779-29-a.fatoum@pengutronix.de> (raw)
In-Reply-To: <20210619045055.779-1-a.fatoum@pengutronix.de>

There will likely not be a use case for having neural network
accelerator driver support within barebox. Still the driver requires a
reset sequence, which is not yet supported by vendor kernel's or known
forks. Until Linux can take care of this itself, add a simple driver
that gets some of the peripherals out of reset.

There also enables unconditionally some of the clocks that the vendor
kernel may depend on. Hopefully, in future, the whole driver can be
dropped when the kernel starts to do clock and reset control itself.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/misc/Kconfig           | 10 ++++
 drivers/misc/Makefile          |  1 +
 drivers/misc/starfive-pwrseq.c | 92 ++++++++++++++++++++++++++++++++++
 3 files changed, 103 insertions(+)
 create mode 100644 drivers/misc/starfive-pwrseq.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 87674a2a29f9..7426dfc46398 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -42,4 +42,14 @@ config ACPI_TEST
 	help
 	  This is a simple Test driver to test the ACPI bus.
 
+config STARFIVE_PWRSEQ
+	bool "StarFive power sequencing driver"
+	depends on SOC_STARFIVE
+	help
+	  This driver sets up a number of StarFive peripherals not matched
+	  by more specific barebox drivers by deasserting reset lines, muxing
+	  pins and/or enabling clocks. Peripherals set up by this can then
+	  be accessed over /dev/mem or used from kernels which still depend
+	  on bootloader for initialization.
+
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 4d92465a1e5e..36743e6ae6a3 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_STATE_DRV)		+= state.o
 obj-$(CONFIG_DEV_MEM)		+= mem.o
 obj-$(CONFIG_UBOOTVAR)		+= ubootvar.o
 obj-$(CONFIG_ACPI_TEST)		+= acpi-test.o
+obj-$(CONFIG_STARFIVE_PWRSEQ)	+= starfive-pwrseq.o
diff --git a/drivers/misc/starfive-pwrseq.c b/drivers/misc/starfive-pwrseq.c
new file mode 100644
index 000000000000..6236547bc568
--- /dev/null
+++ b/drivers/misc/starfive-pwrseq.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Ahmad Fatoum, Pengutronix
+ */
+
+#include <driver.h>
+#include <init.h>
+#include <linux/reset.h>
+#include <dt-bindings/clock/starfive-jh7100.h>
+#include <linux/clk.h>
+
+struct starfive_pwrseq {
+	const char **names;
+};
+
+static int starfive_pwrseq_probe(struct device_d *dev)
+{
+	int ret;
+
+	ret = device_reset_all(dev);
+	if (ret)
+		return ret;
+
+	return of_platform_populate(dev->device_node, NULL, dev);
+}
+
+static struct of_device_id starfive_pwrseq_dt_ids[] = {
+	{ .compatible = "starfive,axi-dma" },
+	{ .compatible = "cm,cm521-vpu" },
+	{ .compatible = "starfive,vic-sec" },
+	{ .compatible = "sfc,tempsensor" },
+	{ .compatible = "cm,codaj12-jpu-1" },
+	{ .compatible = "cdns,xrp" },
+	{ .compatible = "starfive,nne50" },
+	{ .compatible = "nvidia,nvdla_os_initial" },
+	{ .compatible = "starfive,spi2ahb" },
+	{ /* sentinel */ }
+};
+
+static struct driver_d starfive_pwrseq_driver = {
+	.name	= "starfive_pwrseq",
+	.probe	= starfive_pwrseq_probe,
+	.of_compatible = starfive_pwrseq_dt_ids,
+};
+
+static const int clks[] = {
+	CLK_VDEC_AXI, CLK_VDECBRG_MAIN, CLK_VDEC_BCLK, CLK_VDEC_CCLK, CLK_VDEC_APB,
+	CLK_JPEG_AXI, CLK_JPEG_CCLK, CLK_JPEG_APB,
+	CLK_DLA_AXI, CLK_DLANOC_AXI, CLK_DLA_APB, CLK_NNENOC_AXI, CLK_DLASLV_AXI,
+	CLK_VENC_AXI, CLK_VENCBRG_MAIN, CLK_VENC_BCLK, CLK_VENC_CCLK, CLK_VENC_APB,
+	CLK_SGDMA1P_AXI,
+	CLK_DMA2PNOC_AXI, CLK_SGDMA2P_AXI, CLK_SGDMA2P_AHB,
+	CLK_SDIO0_AHB,
+	CLK_SDIO1_AHB,
+	CLK_SPI2AHB_AHB, CLK_SPI2AHB_CORE,
+	CLK_EZMASTER_AHB,
+	CLK_SEC_AHB, CLK_AES, CLK_SHA, CLK_PKA,
+	CLK_UART0_APB, CLK_UART0_CORE,
+	CLK_UART1_APB, CLK_UART1_CORE,
+	CLK_UART2_APB, CLK_UART2_CORE,
+	CLK_UART3_APB, CLK_UART3_CORE,
+	CLK_SPI0_APB, CLK_SPI0_CORE,
+	CLK_SPI1_APB, CLK_SPI1_CORE,
+	CLK_SPI2_APB, CLK_SPI2_CORE,
+	CLK_SPI3_APB, CLK_SPI3_CORE,
+	CLK_I2C0_APB, CLK_I2C0_CORE,
+	CLK_I2C1_APB, CLK_I2C1_CORE,
+	CLK_I2C2_APB, CLK_I2C2_CORE,
+	CLK_I2C3_APB, CLK_I2C3_CORE,
+	CLK_VP6INTC_APB,
+	CLK_TEMP_APB, CLK_TEMP_SENSE,
+
+	CLK_END
+};
+
+static int __init starfive_pwrseq_driver_register(void)
+{
+	struct of_phandle_args clkspec;
+	int i;
+
+	clkspec.args_count = 1;
+	clkspec.np = of_find_compatible_node(NULL, NULL, "starfive,jh7100-clkgen");
+	if (clkspec.np) {
+		for (i = 0; clks[i] != CLK_END; i++) {
+			clkspec.args[0] = clks[i];
+			clk_enable(of_clk_get_from_provider(&clkspec));
+		}
+	}
+
+	return platform_driver_register(&starfive_pwrseq_driver);
+}
+device_initcall(starfive_pwrseq_driver_register);
-- 
2.29.2


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  parent reply	other threads:[~2021-06-19  4:54 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-19  4:50 [PATCH v2 00/29] RISC-V: add BeagleV Beta board support Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 01/29] clocksource: RISC-V: demote probe success messages to debug level Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 02/29] RISC-V: virt: select only one timer Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 03/29] RISC-V: extend multi-image to support both S- and M-Mode Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 04/29] RISC-V: cpuinfo: return some output for non-SBI systems as well Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 05/29] RISC-V: S-Mode: propagate Hart ID Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 06/29] RISC-V: erizo: make it easier to reuse ns16550 debug_ll Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 07/29] RISC-V: socs: add Kconfig entry for StarFive JH7100 Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 08/29] nvmem: add StarFive OTP support Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 09/29] RISC-V: dma: support multiple dma_alloc_coherent backends Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 10/29] RISC-V: add exception support Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 11/29] RISC-V: support incoherent I-Cache Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 12/29] drivers: soc: sifive: add basic L2 cache controller driver Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 13/29] soc: starfive: add support for JH7100 incoherent interconnect Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 14/29] soc: sifive: l2_cache: enable maximum available cache ways Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 15/29] net: designware: fix non-1:1 mapped 64-bit systems Ahmad Fatoum
2021-06-21  7:25   ` Sascha Hauer
2021-06-21  7:33     ` Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 16/29] net: designware: add support for IP integrated into StarFive SoC Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 17/29] mci: allocate DMA-able memory Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 18/29] mci: allocate sector_buf on demand Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 19/29] dma: allocate 32-byte aligned buffers by default Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 20/29] mci: dw_mmc: add optional reset line Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 21/29] mci: dw_mmc: match against StarFive MMC compatibles Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 22/29] clk: add initial StarFive clock support Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 23/29] reset: add StarFive reset controller driver Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 24/29] watchdog: add StarFive watchdog driver Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 25/29] hw_random: add driver for RNG on StarFive SoC Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 26/29] reset: add device_reset_all helper Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 27/29] gpio: add support for StarFive GPIO controller Ahmad Fatoum
2021-06-19  4:50 ` Ahmad Fatoum [this message]
2021-06-19  4:50 ` [PATCH v2 29/29] RISC-V: StarFive: add board support for BeagleV Starlight Ahmad Fatoum
2021-06-21  9:11 ` [PATCH v2 00/29] RISC-V: add BeagleV Beta board support Sascha Hauer

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