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From: Sascha Hauer <sha@pengutronix.de>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH v2 15/29] net: designware: fix non-1:1 mapped 64-bit systems
Date: Mon, 21 Jun 2021 09:25:58 +0200	[thread overview]
Message-ID: <20210621072558.GM9782@pengutronix.de> (raw)
In-Reply-To: <20210619045055.779-16-a.fatoum@pengutronix.de>

On Sat, Jun 19, 2021 at 06:50:41AM +0200, Ahmad Fatoum wrote:
> drivers/net/designware.c handles the older Designware < 4.x MAC IPs,
> which do not support DMA beyond 32-bit. They are still being integrated
> into SoCs with 64-bit CPUs like the StarFive JH7100, which additionally
> needs a non 1:1 mapping for coherent DMA.
> 
> Fix the driver to support such usage. The driver still has the assumption
> that barebox core will only pass it 32-bit pointers. This is now made
> explicit by returning error codes when the DMA mask is violated.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  arch/riscv/include/asm/io.h | 10 +++++++
>  drivers/net/designware.c    | 57 ++++++++++++++++++++++---------------
>  drivers/net/designware.h    | 28 +++++++++++++++---
>  3 files changed, 68 insertions(+), 27 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> index 3cdea7fcace1..795e670e3b9b 100644
> --- a/arch/riscv/include/asm/io.h
> +++ b/arch/riscv/include/asm/io.h
> @@ -5,4 +5,14 @@
>  
>  #include <asm-generic/io.h>
>  
> +static inline void *phys_to_virt(unsigned long phys)
> +{
> +	return (void *)phys;
> +}
> +
> +static inline unsigned long virt_to_phys(volatile void *mem)
> +{
> +	return (unsigned long)mem;
> +}
> +
>  #endif /* __ASM_RISCV_IO_H */
> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
> index 0ee6d3d78ac7..559e202c29ce 100644
> --- a/drivers/net/designware.c
> +++ b/drivers/net/designware.c
> @@ -104,15 +104,15 @@ static void tx_descs_init(struct eth_device *dev)
>  {
>  	struct dw_eth_dev *priv = dev->priv;
>  	struct eth_dma_regs *dma_p = priv->dma_regs_p;
> -	struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
> +	struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable_cpu[0];
>  	char *txbuffs = &priv->txbuffs[0];
>  	struct dmamacdescr *desc_p;
>  	u32 idx;
>  
>  	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
>  		desc_p = &desc_table_p[idx];
> -		desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
> -		desc_p->dmamac_next = &desc_table_p[idx + 1];
> +		desc_p->dmamac_addr = virt_to_phys(&txbuffs[idx * CONFIG_ETH_BUFSIZE]);
> +		desc_p->dmamac_next = tx_dma_addr(priv, &desc_table_p[idx + 1]);
>  
>  		if (priv->enh_desc) {
>  			desc_p->txrx_status &= ~(DESC_ENH_TXSTS_TXINT | DESC_ENH_TXSTS_TXLAST |
> @@ -130,9 +130,9 @@ static void tx_descs_init(struct eth_device *dev)
>  	}
>  
>  	/* Correcting the last pointer of the chain */
> -	desc_p->dmamac_next = &desc_table_p[0];
> +	desc_p->dmamac_next = tx_dma_addr(priv, &desc_table_p[0]);
>  
> -	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
> +	writel(desc_p->dmamac_next, &dma_p->txdesclistaddr);
>  	priv->tx_currdescnum = 0;
>  }
>  
> @@ -140,15 +140,15 @@ static void rx_descs_init(struct eth_device *dev)
>  {
>  	struct dw_eth_dev *priv = dev->priv;
>  	struct eth_dma_regs *dma_p = priv->dma_regs_p;
> -	struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
> +	struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable_cpu[0];
>  	char *rxbuffs = &priv->rxbuffs[0];
>  	struct dmamacdescr *desc_p;
>  	u32 idx;
>  
>  	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
>  		desc_p = &desc_table_p[idx];
> -		desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
> -		desc_p->dmamac_next = &desc_table_p[idx + 1];
> +		desc_p->dmamac_addr = virt_to_phys(&rxbuffs[idx * CONFIG_ETH_BUFSIZE]);

You have both the DMA and virtual addresses available when allocating
the memory. I think you should use this information rather than
introducing the need for a virt_to_phys() phys_to_virt() pair.

> @@ -276,7 +276,7 @@ static int dwc_ether_send(struct eth_device *dev, void *packet, int length)
>  	struct dw_eth_dev *priv = dev->priv;
>  	struct eth_dma_regs *dma_p = priv->dma_regs_p;
>  	u32 owndma, desc_num = priv->tx_currdescnum;
> -	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
> +	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable_cpu[desc_num];
>  
>  	owndma = priv->enh_desc ? DESC_ENH_TXSTS_OWNBYDMA : DESC_TXSTS_OWNBYDMA;
>  	/* Check if the descriptor is owned by CPU */
> @@ -285,8 +285,8 @@ static int dwc_ether_send(struct eth_device *dev, void *packet, int length)
>  		return -1;
>  	}
>  
> -	memcpy((void *)desc_p->dmamac_addr, packet, length);
> -	dma_sync_single_for_device((unsigned long)desc_p->dmamac_addr, length,
> +	memcpy(dmamac_addr(desc_p), packet, length);
> +	dma_sync_single_for_device(desc_p->dmamac_addr, length,
>  				   DMA_TO_DEVICE);

Rather use dma_map_single() here?

Sascha


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  reply	other threads:[~2021-06-21  7:32 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-19  4:50 [PATCH v2 00/29] RISC-V: add BeagleV Beta board support Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 01/29] clocksource: RISC-V: demote probe success messages to debug level Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 02/29] RISC-V: virt: select only one timer Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 03/29] RISC-V: extend multi-image to support both S- and M-Mode Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 04/29] RISC-V: cpuinfo: return some output for non-SBI systems as well Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 05/29] RISC-V: S-Mode: propagate Hart ID Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 06/29] RISC-V: erizo: make it easier to reuse ns16550 debug_ll Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 07/29] RISC-V: socs: add Kconfig entry for StarFive JH7100 Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 08/29] nvmem: add StarFive OTP support Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 09/29] RISC-V: dma: support multiple dma_alloc_coherent backends Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 10/29] RISC-V: add exception support Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 11/29] RISC-V: support incoherent I-Cache Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 12/29] drivers: soc: sifive: add basic L2 cache controller driver Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 13/29] soc: starfive: add support for JH7100 incoherent interconnect Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 14/29] soc: sifive: l2_cache: enable maximum available cache ways Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 15/29] net: designware: fix non-1:1 mapped 64-bit systems Ahmad Fatoum
2021-06-21  7:25   ` Sascha Hauer [this message]
2021-06-21  7:33     ` Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 16/29] net: designware: add support for IP integrated into StarFive SoC Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 17/29] mci: allocate DMA-able memory Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 18/29] mci: allocate sector_buf on demand Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 19/29] dma: allocate 32-byte aligned buffers by default Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 20/29] mci: dw_mmc: add optional reset line Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 21/29] mci: dw_mmc: match against StarFive MMC compatibles Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 22/29] clk: add initial StarFive clock support Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 23/29] reset: add StarFive reset controller driver Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 24/29] watchdog: add StarFive watchdog driver Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 25/29] hw_random: add driver for RNG on StarFive SoC Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 26/29] reset: add device_reset_all helper Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 27/29] gpio: add support for StarFive GPIO controller Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 28/29] misc: add power sequencing driver for initializing StarFive peripherals Ahmad Fatoum
2021-06-19  4:50 ` [PATCH v2 29/29] RISC-V: StarFive: add board support for BeagleV Starlight Ahmad Fatoum
2021-06-21  9:11 ` [PATCH v2 00/29] RISC-V: add BeagleV Beta board support Sascha Hauer

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