From: Ahmad Fatoum <a.fatoum@pengutronix.de> To: barebox@lists.infradead.org Cc: Ahmad Fatoum <a.fatoum@pengutronix.de> Subject: [PATCH 11/20] dma: support marking SRAM for coherent DMA use Date: Mon, 31 May 2021 09:38:12 +0200 [thread overview] Message-ID: <20210531073821.15257-12-a.fatoum@pengutronix.de> (raw) In-Reply-To: <20210531073821.15257-1-a.fatoum@pengutronix.de> The RISC-V architecture allows overriding the dma_alloc_coherent and dma_free_coherent. Allow this to be controlled by device tree. Cache-coherent SoCs won't need this, but incoherent ones that have uncached regions can register them here. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> --- common/Kconfig | 4 ++ common/Makefile | 3 +- drivers/dma/Kconfig | 6 ++ drivers/dma/Makefile | 1 + drivers/dma/coherent-pool.c | 120 ++++++++++++++++++++++++++++++++++++ 5 files changed, 133 insertions(+), 1 deletion(-) create mode 100644 drivers/dma/coherent-pool.c diff --git a/common/Kconfig b/common/Kconfig index ce349d4ebbf6..dbbcbb946fff 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -303,6 +303,9 @@ config EXPERIMENTAL bool prompt "Prompt for experimental code" +config TLSF + bool + choice prompt "malloc implementation" @@ -311,6 +314,7 @@ config MALLOC_DLMALLOC config MALLOC_TLSF bool "tlsf" + select TLSF config MALLOC_DUMMY bool "dummy malloc" diff --git a/common/Makefile b/common/Makefile index 382a4f661f67..0777d2030c99 100644 --- a/common/Makefile +++ b/common/Makefile @@ -40,7 +40,8 @@ obj-$(CONFIG_GLOBALVAR) += globalvar.o obj-$(CONFIG_GREGORIAN_CALENDER) += date.o obj-$(CONFIG_KALLSYMS) += kallsyms.o obj-$(CONFIG_MALLOC_DLMALLOC) += dlmalloc.o -obj-$(CONFIG_MALLOC_TLSF) += tlsf_malloc.o tlsf.o calloc.o +obj-$(CONFIG_TLSF) += tlsf.o +obj-$(CONFIG_MALLOC_TLSF) += tlsf_malloc.o calloc.o KASAN_SANITIZE_tlsf.o := n obj-$(CONFIG_MALLOC_DUMMY) += dummy_malloc.o calloc.o obj-$(CONFIG_MEMINFO) += meminfo.o diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index c75fc8b9811f..6bc915585fbe 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -1,5 +1,11 @@ menu "DMA support" +config DMA_COHERENT_POOLS + bool + depends on RISCV + select TLSF + imply SRAM + config MXS_APBH_DMA tristate "MXS APBH DMA ENGINE" depends on ARCH_IMX23 || ARCH_IMX28 || ARCH_IMX6 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 49d6d6573f4f..5503a4af0049 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_MXS_APBH_DMA) += apbh_dma.o obj-$(CONFIG_HAS_DMA) += map.o +obj-$(CONFIG_DMA_COHERENT_POOLS) += coherent-pool.o diff --git a/drivers/dma/coherent-pool.c b/drivers/dma/coherent-pool.c new file mode 100644 index 000000000000..524283be711f --- /dev/null +++ b/drivers/dma/coherent-pool.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + */ + +#define pr_fmt(fmt) "dma-coherent-pool: " fmt + +#include <common.h> +#include <asm/dma.h> +#include <linux/list.h> +#include <errno.h> +#include <tlsf.h> + +struct dma_coherent_pool { + tlsf_t handle; + const struct resource *resource; + struct list_head list; +}; + +static LIST_HEAD(pools); + +static void *pool_alloc_coherent(size_t size, dma_addr_t *dma_handle) +{ + struct dma_coherent_pool *pool; + void *ret = NULL; + + list_for_each_entry(pool, &pools, list) { + ret = tlsf_memalign(pool->handle, DMA_ALIGNMENT, size); + if (!ret) + continue; + } + + BUG_ON(!ret); + + memset(ret, 0, size); + + if (dma_handle) + *dma_handle = (dma_addr_t)ret; + + pr_debug("alloc(%zu) == %p\n", size, ret); + + return ret; +} + +static void pool_free_coherent(void *vaddr, dma_addr_t dma_handle, size_t size) +{ + resource_size_t addr = (resource_size_t)vaddr; + struct dma_coherent_pool *pool; + + list_for_each_entry(pool, &pools, list) { + if (pool->resource->start <= addr && addr <= pool->resource->end) { + tlsf_free(pool->handle, vaddr); + return; + } + } + + pr_warn("freeing invalid region: %p\n", vaddr); +} + +static const struct dma_coherent_ops pool_ops = { + .alloc = pool_alloc_coherent, + .free = pool_free_coherent, +}; + +static int compare_pool_sizes(struct list_head *_a, struct list_head *_b) +{ + struct dma_coherent_pool *a = list_entry(_a, struct dma_coherent_pool, list); + struct dma_coherent_pool *b = list_entry(_b, struct dma_coherent_pool, list); + + if (resource_size(a->resource) > resource_size(b->resource)) + return 1; + if (resource_size(a->resource) < resource_size(b->resource)) + return -1; + return 0; +} + +static int dma_declare_coherent_pool(const struct resource *res) +{ + struct dma_coherent_pool *pool; + tlsf_t handle; + + handle = tlsf_create_with_pool((void *)res->start, resource_size(res)); + if (!handle) + return -EINVAL; + + pool = xmalloc(sizeof(*pool)); + pool->handle = handle; + pool->resource = res; + + list_add_sort(&pool->list, &pools, compare_pool_sizes); + + dma_set_coherent_ops(&pool_ops); + + pr_debug("registered pool @(%llx-%llx)\n", (u64)res->start, (u64)res->end); + + return 0; +} + +static int coherent_dma_pool_probe(struct device_d *dev) +{ + struct resource *res; + + res = dev_get_resource(dev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) + return PTR_ERR(res); + + return dma_declare_coherent_pool(res); +} + +static struct of_device_id coherent_dma_pool_dt_ids[] = { + { .compatible = "barebox,coherent-dma-pool", }, + { /* sentinel */ } +}; + +static struct driver_d coherent_dma_pool_driver = { + .name = "coherent-dma-pool", + .probe = coherent_dma_pool_probe, + .of_compatible = coherent_dma_pool_dt_ids, +}; +coredevice_platform_driver(coherent_dma_pool_driver); -- 2.29.2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
next prev parent reply other threads:[~2021-05-31 7:42 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-31 7:38 [PATCH 00/20] RISC-V: prepare for BeagleV pre-production board support Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 01/20] RISC-V: socs: add Kconfig entry for StarFive JH7100 Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 02/20] net: designware: add support for IP integrated into StarFive SoC Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 03/20] mfd: add TI TPS65086 PMIC restart driver Ahmad Fatoum 2021-06-07 6:44 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 04/20] mtd: spi-nor: cadence: fix 64-bit issues Ahmad Fatoum 2021-06-07 6:51 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 05/20] nvmem: add StarFive OTP support Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 06/20] RISC-V: dma: support multiple dma_alloc_coherent backends Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 07/20] RISC-V: support incoherent I-Cache Ahmad Fatoum 2021-05-31 7:40 ` Ahmad Fatoum 2021-06-07 7:33 ` Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 08/20] soc: add support for StarFive JH7100 incoherent interconnect Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 09/20] soc: sifive: l2_cache: enable maximum available cache ways Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 10/20] net: designware: fix 64-bit incompatibilities Ahmad Fatoum 2021-05-31 7:38 ` Ahmad Fatoum [this message] 2021-06-07 7:34 ` [PATCH 11/20] dma: support marking SRAM for coherent DMA use Sascha Hauer 2021-06-07 7:40 ` Ahmad Fatoum 2021-06-07 7:39 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 12/20] mci: allocate DMA-able memory Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 13/20] mci: allocate sector_buf on demand Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 14/20] dma: allocate 32-byte aligned buffers by default Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 15/20] mci: dw_mmc: enable use on 64-bit CPUs Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 16/20] mci: dw_mmc: match against generic "snps, dw-mshc" compatible Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 17/20] clk: add initial StarFive clock support Ahmad Fatoum 2021-05-31 8:41 ` Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 18/20] reset: add StarFive reset controller driver Ahmad Fatoum 2021-06-07 8:00 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 19/20] watchdog: add StarFive watchdog driver Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 20/20] hw_random: add driver for RNG on StarFive SoC Ahmad Fatoum
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