From: Ahmad Fatoum <a.fatoum@pengutronix.de> To: barebox@lists.infradead.org Cc: Ahmad Fatoum <a.fatoum@pengutronix.de> Subject: [PATCH 15/20] mci: dw_mmc: enable use on 64-bit CPUs Date: Mon, 31 May 2021 09:38:16 +0200 [thread overview] Message-ID: <20210531073821.15257-16-a.fatoum@pengutronix.de> (raw) In-Reply-To: <20210531073821.15257-1-a.fatoum@pengutronix.de> Provided that all DMA addresses can be safely truncated to 32-bit, the driver is already usable on 64-bit CPUs. Silence the warnings and add a check to ensure that coherent DMA addresses are indeed 32-bit. arch code will need to make sure that dma_alloc() returns DMA memory suitable for all DMA masters. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> --- drivers/mci/dw_mmc.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/mci/dw_mmc.c b/drivers/mci/dw_mmc.c index 7979568841fc..db8aa9473458 100644 --- a/drivers/mci/dw_mmc.c +++ b/drivers/mci/dw_mmc.c @@ -124,12 +124,12 @@ static int dwmci_prepare_data_dma(struct dwmci_host *host, dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); - dwmci_writel(host, DWMCI_DBADDR, (uint32_t)desc); + dwmci_writel(host, DWMCI_DBADDR, virt_to_phys(desc)); if (data->flags & MMC_DATA_READ) - start_addr = (uint32_t)data->dest; + start_addr = virt_to_phys(data->dest); else - start_addr = (uint32_t)data->src; + start_addr = virt_to_phys((void *)data->src); do { flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH; @@ -145,7 +145,7 @@ static int dwmci_prepare_data_dma(struct dwmci_host *host, desc->flags = flags; desc->cnt = cnt; desc->addr = start_addr + (i * PAGE_SIZE); - desc->next_addr = (uint32_t)(desc + 1); + desc->next_addr = virt_to_phys(desc + 1); dev_dbg(host->mci.hw_dev, "desc@ 0x%p 0x%08x 0x%08x 0x%08x 0x%08x\n", desc, flags, cnt, desc->addr, desc->next_addr); @@ -290,10 +290,10 @@ dwmci_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data) num_bytes = data->blocks * data->blocksize; if (data->flags & MMC_DATA_WRITE) - dma_sync_single_for_device((unsigned long)data->src, + dma_sync_single_for_device(virt_to_phys((void *)data->src), num_bytes, DMA_TO_DEVICE); else - dma_sync_single_for_device((unsigned long)data->dest, + dma_sync_single_for_device(virt_to_phys(data->dest), num_bytes, DMA_FROM_DEVICE); ret = dwmci_prepare_data(host, data); @@ -400,10 +400,10 @@ dwmci_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data) dwmci_writel(host, DWMCI_CTRL, ctrl); if (data->flags & MMC_DATA_WRITE) - dma_sync_single_for_cpu((unsigned long)data->src, + dma_sync_single_for_cpu(virt_to_phys((void *)data->src), num_bytes, DMA_TO_DEVICE); else - dma_sync_single_for_cpu((unsigned long)data->dest, + dma_sync_single_for_cpu(virt_to_phys(data->dest), num_bytes, DMA_FROM_DEVICE); } } @@ -547,6 +547,9 @@ static int dw_mmc_probe(struct device_d *dev) struct resource *iores; struct dwmci_host *host; struct dw_mmc_platform_data *pdata = dev->platform_data; + dma_addr_t idmac; + + dma_set_mask(dev, DMA_BIT_MASK(32)); host = xzalloc(sizeof(*host)); @@ -567,7 +570,12 @@ static int dw_mmc_probe(struct device_d *dev) host->ioaddr = IOMEM(iores->start); host->idmac = dma_alloc_coherent(sizeof(*host->idmac) * DW_MMC_NUM_IDMACS, - DMA_ADDRESS_BROKEN); + &idmac); /* still DMA_ADDRESS_BROKEN */ + + if (dma_mapping_error(dev, idmac)) { + dev_err(dev, "allocated buffer violates DMA mask\n"); + return -ENOMEM; + } host->mci.send_cmd = dwmci_cmd; host->mci.set_ios = dwmci_set_ios; -- 2.29.2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
next prev parent reply other threads:[~2021-05-31 7:40 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-31 7:38 [PATCH 00/20] RISC-V: prepare for BeagleV pre-production board support Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 01/20] RISC-V: socs: add Kconfig entry for StarFive JH7100 Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 02/20] net: designware: add support for IP integrated into StarFive SoC Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 03/20] mfd: add TI TPS65086 PMIC restart driver Ahmad Fatoum 2021-06-07 6:44 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 04/20] mtd: spi-nor: cadence: fix 64-bit issues Ahmad Fatoum 2021-06-07 6:51 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 05/20] nvmem: add StarFive OTP support Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 06/20] RISC-V: dma: support multiple dma_alloc_coherent backends Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 07/20] RISC-V: support incoherent I-Cache Ahmad Fatoum 2021-05-31 7:40 ` Ahmad Fatoum 2021-06-07 7:33 ` Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 08/20] soc: add support for StarFive JH7100 incoherent interconnect Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 09/20] soc: sifive: l2_cache: enable maximum available cache ways Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 10/20] net: designware: fix 64-bit incompatibilities Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 11/20] dma: support marking SRAM for coherent DMA use Ahmad Fatoum 2021-06-07 7:34 ` Sascha Hauer 2021-06-07 7:40 ` Ahmad Fatoum 2021-06-07 7:39 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 12/20] mci: allocate DMA-able memory Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 13/20] mci: allocate sector_buf on demand Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 14/20] dma: allocate 32-byte aligned buffers by default Ahmad Fatoum 2021-05-31 7:38 ` Ahmad Fatoum [this message] 2021-05-31 7:38 ` [PATCH 16/20] mci: dw_mmc: match against generic "snps, dw-mshc" compatible Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 17/20] clk: add initial StarFive clock support Ahmad Fatoum 2021-05-31 8:41 ` Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 18/20] reset: add StarFive reset controller driver Ahmad Fatoum 2021-06-07 8:00 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 19/20] watchdog: add StarFive watchdog driver Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 20/20] hw_random: add driver for RNG on StarFive SoC Ahmad Fatoum
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