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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: Antony Pavlov <antonynpavlov@gmail.com>
Cc: "barebox@lists.infradead.org" <barebox@lists.infradead.org>
Subject: Re: [PATCH 07/20] RISC-V: support incoherent I-Cache
Date: Mon, 7 Jun 2021 09:33:50 +0200	[thread overview]
Message-ID: <79eb9d75-f2e8-ee6b-9490-9f2c22c5e2de@pengutronix.de> (raw)
In-Reply-To: <d193ad83-21f2-cbc5-a8d9-01ffa6cbe149@pengutronix.de>

On 31.05.21 09:40, Ahmad Fatoum wrote:
> Hello Antony,
> 
> On 31.05.21 09:38, Ahmad Fatoum wrote:
>> SiFive SoCs have separate I-Caches that require self-modifying code
>> like barebox' relocation and PBL extraction code to do cache
>> maintenance. Implement sync_caches_for_execution and use it where
>> appropriate.
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---

>> +void sync_caches_for_execution(void)
>> +{
>> +	if (IS_ENABLED(CONFIG_HAS_CACHE))
>> +		asm volatile ("fence.i" ::: "memory");
> 
> If Erizo on FPGA chokes on this, we can have it pass
> along a feature flag from PBL that says it doesn't
> need cache maintenance. Please advise.

I now skip over fence.i in the exception handler, so it should be ok
to call this, even on systems that lack Zifencei ISA extension.

I'll send out a v2 soon.

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  reply	other threads:[~2021-06-07  7:35 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-31  7:38 [PATCH 00/20] RISC-V: prepare for BeagleV pre-production board support Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 01/20] RISC-V: socs: add Kconfig entry for StarFive JH7100 Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 02/20] net: designware: add support for IP integrated into StarFive SoC Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 03/20] mfd: add TI TPS65086 PMIC restart driver Ahmad Fatoum
2021-06-07  6:44   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 04/20] mtd: spi-nor: cadence: fix 64-bit issues Ahmad Fatoum
2021-06-07  6:51   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 05/20] nvmem: add StarFive OTP support Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 06/20] RISC-V: dma: support multiple dma_alloc_coherent backends Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 07/20] RISC-V: support incoherent I-Cache Ahmad Fatoum
2021-05-31  7:40   ` Ahmad Fatoum
2021-06-07  7:33     ` Ahmad Fatoum [this message]
2021-05-31  7:38 ` [PATCH 08/20] soc: add support for StarFive JH7100 incoherent interconnect Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 09/20] soc: sifive: l2_cache: enable maximum available cache ways Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 10/20] net: designware: fix 64-bit incompatibilities Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 11/20] dma: support marking SRAM for coherent DMA use Ahmad Fatoum
2021-06-07  7:34   ` Sascha Hauer
2021-06-07  7:40     ` Ahmad Fatoum
2021-06-07  7:39   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 12/20] mci: allocate DMA-able memory Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 13/20] mci: allocate sector_buf on demand Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 14/20] dma: allocate 32-byte aligned buffers by default Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 15/20] mci: dw_mmc: enable use on 64-bit CPUs Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 16/20] mci: dw_mmc: match against generic "snps, dw-mshc" compatible Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 17/20] clk: add initial StarFive clock support Ahmad Fatoum
2021-05-31  8:41   ` Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 18/20] reset: add StarFive reset controller driver Ahmad Fatoum
2021-06-07  8:00   ` Sascha Hauer
2021-05-31  7:38 ` [PATCH 19/20] watchdog: add StarFive watchdog driver Ahmad Fatoum
2021-05-31  7:38 ` [PATCH 20/20] hw_random: add driver for RNG on StarFive SoC Ahmad Fatoum

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