From: Ahmad Fatoum <a.fatoum@pengutronix.de> To: barebox@lists.infradead.org Cc: Ahmad Fatoum <a.fatoum@pengutronix.de> Subject: [PATCH 02/20] net: designware: add support for IP integrated into StarFive SoC Date: Mon, 31 May 2021 09:38:03 +0200 [thread overview] Message-ID: <20210531073821.15257-3-a.fatoum@pengutronix.de> (raw) In-Reply-To: <20210531073821.15257-1-a.fatoum@pengutronix.de> The Designware MAC on the StarFive jh7100 needs some special speed configuration. Match against a new starfive,stmmac compatible that describes that. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> --- drivers/net/Kconfig | 8 +++ drivers/net/Makefile | 1 + drivers/net/designware.c | 7 +- drivers/net/designware.h | 1 + drivers/net/designware_starfive.c | 109 ++++++++++++++++++++++++++++++ include/soc/starfive/sysmain.h | 15 ++++ 6 files changed, 138 insertions(+), 3 deletions(-) create mode 100644 drivers/net/designware_starfive.c create mode 100644 include/soc/starfive/sysmain.h diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 0d55ea7a3b60..ed018dbf9a67 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -82,6 +82,14 @@ config DRIVER_NET_DESIGNWARE_SOCFPGA This option enables support for the Synopsys Designware Core Univesal MAC 10M/100M/1G ethernet IP on SoCFPGA. +config DRIVER_NET_DESIGNWARE_STARFIVE + bool "Designware Universal MAC ethernet driver for StarFive platforms" + depends on SOC_STARFIVE || COMPILE_TEST + select MFD_SYSCON + help + This option enables support for the Synopsys + Designware Core Univesal MAC 10M/100M/1G ethernet IP on StarFive. + endif config DRIVER_NET_DESIGNWARE_EQOS diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 656d45a868a5..0ce310de05c2 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_DRIVER_NET_DAVINCI_EMAC) += davinci_emac.o obj-$(CONFIG_DRIVER_NET_DESIGNWARE) += designware.o obj-$(CONFIG_DRIVER_NET_DESIGNWARE_GENERIC) += designware_generic.o obj-$(CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA) += designware_socfpga.o +obj-$(CONFIG_DRIVER_NET_DESIGNWARE_STARFIVE) += designware_starfive.o obj-$(CONFIG_DRIVER_NET_DESIGNWARE_EQOS) += designware_eqos.o obj-$(CONFIG_DRIVER_NET_DESIGNWARE_STM32) += designware_stm32.o obj-$(CONFIG_DRIVER_NET_DESIGNWARE_TEGRA186) += designware_tegra186.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 0ee6d3d78ac7..e815d74ce9b8 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -457,11 +457,12 @@ struct dw_eth_dev *dwc_drv_probe(struct device_d *dev) if (ret) return ERR_PTR(ret); - if (drvdata && drvdata->enh_desc) + if (drvdata) { priv->enh_desc = drvdata->enh_desc; - else + priv->fix_mac_speed = drvdata->fix_mac_speed; + } else { dev_warn(dev, "No drvdata specified\n"); - + } if (pdata) { priv->phy_addr = pdata->phy_addr; diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 0a6a6bf1a497..ef3705b1e387 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -35,6 +35,7 @@ struct dw_eth_dev { struct dw_eth_drvdata { bool enh_desc; + void (*fix_mac_speed)(int speed); void *priv; }; diff --git a/drivers/net/designware_starfive.c b/drivers/net/designware_starfive.c new file mode 100644 index 000000000000..e7e3fe5fb364 --- /dev/null +++ b/drivers/net/designware_starfive.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 Ahmad Fatoum, Pengutronix + */ + +#include <common.h> +#include <init.h> +#include <linux/reset.h> +#include <linux/clk.h> +#include <mfd/syscon.h> +#include <soc/starfive/sysmain.h> +#include "designware.h" + +/* + * GMAC_GTXCLK + * bit name access default description + * [31] _gmac_gtxclk enable RW 0x0 "1:enable; 0:disable" + * [30] reserved - 0x0 reserved + * [29:8] reserved - 0x0 reserved + * [7:0] gmac_gtxclk ratio RW 0x4 divider value + * + * 1000M: gtxclk@125M => 500/125 = 0x4 + * 100M: gtxclk@25M => 500/25 = 0x14 + * 10M: gtxclk@2.5M => 500/2.5 = 0xc8 + */ + +#define CLKGEN_BASE 0x11800000 +#define CLKGEN_GMAC_GTXCLK_OFFSET 0x1EC +#define CLKGEN_GMAC_GTXCLK_ADDR (CLKGEN_BASE + CLKGEN_GMAC_GTXCLK_OFFSET) + + +#define CLKGEN_125M_DIV 0x4 +#define CLKGEN_25M_DIV 0x14 +#define CLKGEN_2_5M_DIV 0xc8 + +static void dwmac_fixed_speed(int speed) +{ + /* TODO: move this into clk driver */ + void __iomem *addr = IOMEM(CLKGEN_GMAC_GTXCLK_ADDR); + u32 value; + + value = readl(addr) & (~0x000000FF); + + switch (speed) { + case SPEED_1000: value |= CLKGEN_125M_DIV; break; + case SPEED_100: value |= CLKGEN_25M_DIV; break; + case SPEED_10: value |= CLKGEN_2_5M_DIV; break; + default: return; + } + + writel(value, addr); +} + +static struct dw_eth_drvdata starfive_drvdata = { + .enh_desc = 1, + .fix_mac_speed = dwmac_fixed_speed, +}; + +static int starfive_dwc_ether_probe(struct device_d *dev) +{ + struct dw_eth_dev *dwc; + struct regmap *regmap; + int ret; + struct clk_bulk_data clks[] = { + { .id = "ptp_ref" }, + { .id = "tx" }, + }; + + regmap = syscon_regmap_lookup_by_phandle(dev->device_node, "starfive,sysmain"); + if (IS_ERR(regmap)) { + dev_err(dev, "Could not get starfive,sysmain node\n"); + return PTR_ERR(regmap); + } + + ret = clk_bulk_get(dev, ARRAY_SIZE(clks), clks); + if (ret) + return ret; + + ret = clk_bulk_enable(ARRAY_SIZE(clks), clks); + if (ret < 0) + return ret; + + ret = device_reset(dev); + if (ret) + return ret; + + dwc = dwc_drv_probe(dev); + if (IS_ERR(dwc)) + return PTR_ERR(dwc); + + if (phy_interface_mode_is_rgmii(dwc->interface)) { + regmap_update_bits(regmap, SYSMAIN_GMAC_PHY_INTF_SEL, 0x7, 0x1); + regmap_write(regmap, SYSMAIN_GMAC_GTXCLK_DLYCHAIN_SEL, 0x4); + } + + return 0; +} + +static struct of_device_id starfive_dwc_ether_compatible[] = { + { .compatible = "starfive,stmmac", .data = &starfive_drvdata }, + { /* sentinel */ } +}; + +static struct driver_d starfive_dwc_ether_driver = { + .name = "starfive-designware_eth", + .probe = starfive_dwc_ether_probe, + .of_compatible = starfive_dwc_ether_compatible, +}; +device_platform_driver(starfive_dwc_ether_driver); diff --git a/include/soc/starfive/sysmain.h b/include/soc/starfive/sysmain.h new file mode 100644 index 000000000000..b58f8d9825fd --- /dev/null +++ b/include/soc/starfive/sysmain.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _STARFIVE_SYSMAIN_H_ +#define _STARFIVE_SYSMAIN_H_ + +#define SYSMAIN_PLL0_REG 0x00 +#define SYSMAIN_PLL1_REG 0x04 +#define SYSMAIN_PLL2_REG 0x08 +#define SYSMAIN_PLLS_STAT 0x0c + +#define SYSMAIN_GMAC_PHY_INTF_SEL 0x70 +#define SYSMAIN_GMAC_GTXCLK_DLYCHAIN_SEL 0xC8 + + +#endif //_SYSCON_SYSMAIN_CTRL_MACRO_H_ -- 2.29.2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
next prev parent reply other threads:[~2021-05-31 7:40 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-31 7:38 [PATCH 00/20] RISC-V: prepare for BeagleV pre-production board support Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 01/20] RISC-V: socs: add Kconfig entry for StarFive JH7100 Ahmad Fatoum 2021-05-31 7:38 ` Ahmad Fatoum [this message] 2021-05-31 7:38 ` [PATCH 03/20] mfd: add TI TPS65086 PMIC restart driver Ahmad Fatoum 2021-06-07 6:44 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 04/20] mtd: spi-nor: cadence: fix 64-bit issues Ahmad Fatoum 2021-06-07 6:51 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 05/20] nvmem: add StarFive OTP support Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 06/20] RISC-V: dma: support multiple dma_alloc_coherent backends Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 07/20] RISC-V: support incoherent I-Cache Ahmad Fatoum 2021-05-31 7:40 ` Ahmad Fatoum 2021-06-07 7:33 ` Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 08/20] soc: add support for StarFive JH7100 incoherent interconnect Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 09/20] soc: sifive: l2_cache: enable maximum available cache ways Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 10/20] net: designware: fix 64-bit incompatibilities Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 11/20] dma: support marking SRAM for coherent DMA use Ahmad Fatoum 2021-06-07 7:34 ` Sascha Hauer 2021-06-07 7:40 ` Ahmad Fatoum 2021-06-07 7:39 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 12/20] mci: allocate DMA-able memory Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 13/20] mci: allocate sector_buf on demand Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 14/20] dma: allocate 32-byte aligned buffers by default Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 15/20] mci: dw_mmc: enable use on 64-bit CPUs Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 16/20] mci: dw_mmc: match against generic "snps, dw-mshc" compatible Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 17/20] clk: add initial StarFive clock support Ahmad Fatoum 2021-05-31 8:41 ` Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 18/20] reset: add StarFive reset controller driver Ahmad Fatoum 2021-06-07 8:00 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 19/20] watchdog: add StarFive watchdog driver Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 20/20] hw_random: add driver for RNG on StarFive SoC Ahmad Fatoum
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