From: Ahmad Fatoum <a.fatoum@pengutronix.de> To: barebox@lists.infradead.org Cc: Ahmad Fatoum <a.fatoum@pengutronix.de> Subject: [PATCH 19/20] watchdog: add StarFive watchdog driver Date: Mon, 31 May 2021 09:38:20 +0200 [thread overview] Message-ID: <20210531073821.15257-20-a.fatoum@pengutronix.de> (raw) In-Reply-To: <20210531073821.15257-1-a.fatoum@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> --- drivers/watchdog/Kconfig | 7 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/starfive_wdt.c | 97 +++++++++++++++++++++++++++++++++ 3 files changed, 105 insertions(+) create mode 100644 drivers/watchdog/starfive_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 542659825045..8aeca0bd6f5f 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -148,4 +148,11 @@ config ITCO_WDT NO_REBOOT flag which prevents the watchdog from rebooting the machine. +config STARFIVE_WDT + tristate "StarFive Watchdog Timer" + depends on SOC_STARFIVE && OFDEVICE + help + If you say yes here you get support for the watchdog device + on StarFive SoCs. + endif diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 0b598af40218..4e784b5aaa30 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -18,3 +18,4 @@ obj-$(CONFIG_STPMIC1_WATCHDOG) += stpmic1_wdt.o obj-$(CONFIG_F71808E_WDT) += f71808e_wdt.o obj-$(CONFIG_GPIO_WATCHDOG) += gpio_wdt.o obj-$(CONFIG_ITCO_WDT) += itco_wdt.o +obj-$(CONFIG_STARFIVE_WDT) += starfive_wdt.o diff --git a/drivers/watchdog/starfive_wdt.c b/drivers/watchdog/starfive_wdt.c new file mode 100644 index 000000000000..abe20f7a1a82 --- /dev/null +++ b/drivers/watchdog/starfive_wdt.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2018 Kalray Inc. + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <of.h> +#include <watchdog.h> +#include <linux/reset.h> + +#include <linux/clk.h> +#include <linux/err.h> + +#define WDT_REG_RESET_EN 0x104 +#define WDT_REG_TIMEOUT 0x108 +#define WDT_REG_CONTROL 0x110 +#define WDT_REG_UNLOCK 0x13c + +#define WDT_UNLOCK_KEY 0x378f0765 + +struct starfive_wdt { + uint32_t clk_rate; + struct watchdog wdd; + void __iomem *base; + bool setup; +}; + +static int starfive_wdt_set_timeout(struct watchdog *wdd, unsigned int timeout) +{ + struct starfive_wdt *wd = container_of(wdd, struct starfive_wdt, wdd); + + writel(0, wd->base + WDT_REG_CONTROL); + + if (timeout > 0) { + timeout *= wd->clk_rate; + writel(timeout, wd->base + WDT_REG_TIMEOUT); + writel(1, wd->base + WDT_REG_CONTROL); + } + + return 0; +} + +static int starfive_wdt_drv_probe(struct device_d *dev) +{ + struct starfive_wdt *wd; + struct resource *iores; + struct watchdog *wdd; + struct clk *clk; + int ret; + + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + + wd = xzalloc(sizeof(*wd)); + wd->base = IOMEM(iores->start); + + wd->clk_rate = clk_get_rate(clk); + + ret = device_reset_all(dev); + if (ret) + return ret; + + writel(WDT_UNLOCK_KEY, wd->base + WDT_REG_UNLOCK); + wd->base = IOMEM(iores->start); + /* reset, not interrupt, on timer expiry */ + writel(1, wd->base + WDT_REG_RESET_EN); + + wdd = &wd->wdd; + wdd->name = "starfive_wdt"; + wdd->hwdev = dev; + wdd->set_timeout = starfive_wdt_set_timeout; + wdd->timeout_max = U32_MAX / wd->clk_rate; + + wdd->running = readl(wd->base + WDT_REG_CONTROL) & 1 ? + WDOG_HW_RUNNING : WDOG_HW_NOT_RUNNING; + + return watchdog_register(wdd); +} + +static struct of_device_id starfive_wdt_of_match[] = { + { .compatible = "starfive,wdt", }, + { /* sentinel */ } +}; + +static struct driver_d starfive_wdt_driver = { + .name = "starfive-wdt", + .probe = starfive_wdt_drv_probe, + .of_compatible = starfive_wdt_of_match, +}; +device_platform_driver(starfive_wdt_driver); -- 2.29.2 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
next prev parent reply other threads:[~2021-05-31 7:42 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-31 7:38 [PATCH 00/20] RISC-V: prepare for BeagleV pre-production board support Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 01/20] RISC-V: socs: add Kconfig entry for StarFive JH7100 Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 02/20] net: designware: add support for IP integrated into StarFive SoC Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 03/20] mfd: add TI TPS65086 PMIC restart driver Ahmad Fatoum 2021-06-07 6:44 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 04/20] mtd: spi-nor: cadence: fix 64-bit issues Ahmad Fatoum 2021-06-07 6:51 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 05/20] nvmem: add StarFive OTP support Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 06/20] RISC-V: dma: support multiple dma_alloc_coherent backends Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 07/20] RISC-V: support incoherent I-Cache Ahmad Fatoum 2021-05-31 7:40 ` Ahmad Fatoum 2021-06-07 7:33 ` Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 08/20] soc: add support for StarFive JH7100 incoherent interconnect Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 09/20] soc: sifive: l2_cache: enable maximum available cache ways Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 10/20] net: designware: fix 64-bit incompatibilities Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 11/20] dma: support marking SRAM for coherent DMA use Ahmad Fatoum 2021-06-07 7:34 ` Sascha Hauer 2021-06-07 7:40 ` Ahmad Fatoum 2021-06-07 7:39 ` Sascha Hauer 2021-05-31 7:38 ` [PATCH 12/20] mci: allocate DMA-able memory Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 13/20] mci: allocate sector_buf on demand Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 14/20] dma: allocate 32-byte aligned buffers by default Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 15/20] mci: dw_mmc: enable use on 64-bit CPUs Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 16/20] mci: dw_mmc: match against generic "snps, dw-mshc" compatible Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 17/20] clk: add initial StarFive clock support Ahmad Fatoum 2021-05-31 8:41 ` Ahmad Fatoum 2021-05-31 7:38 ` [PATCH 18/20] reset: add StarFive reset controller driver Ahmad Fatoum 2021-06-07 8:00 ` Sascha Hauer 2021-05-31 7:38 ` Ahmad Fatoum [this message] 2021-05-31 7:38 ` [PATCH 20/20] hw_random: add driver for RNG on StarFive SoC Ahmad Fatoum
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